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Searched refs:EVERGREEN_CRTC3_REGISTER_OFFSET (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Devergreen_reg.h227 #define EVERGREEN_CRTC3_REGISTER_OFFSET (0x111f0 - 0x6df0) macro
H A Dradeon_display.c1506 EVERGREEN_CRTC3_REGISTER_OFFSET, in radeon_afmt_init()
1848 EVERGREEN_CRTC3_REGISTER_OFFSET); in radeon_get_crtc_scanoutpos()
1850 EVERGREEN_CRTC3_REGISTER_OFFSET); in radeon_get_crtc_scanoutpos()
H A Dcik.c6885 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6898 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7237 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); in cik_irq_set()
7253 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, in cik_irq_set()
7305 EVERGREEN_CRTC3_REGISTER_OFFSET); in cik_irq_ack()
7334 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, in cik_irq_ack()
7341 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7343 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
H A Dradeon_device.c680 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); in radeon_card_posted()
H A Devergreen_cs.c1033 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC3_REGISTER_OFFSET, in evergreen_cs_packet_parse_vline()
1041 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, in evergreen_cs_packet_parse_vline()
H A Datombios_crtc.c2243 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; in radeon_atombios_init_crtc()
H A Devergreen.c128 EVERGREEN_CRTC3_REGISTER_OFFSET,
H A Dsi.c145 EVERGREEN_CRTC3_REGISTER_OFFSET,