1 /* 2 * Definitions for the Ethernet registers 3 * 4 * Copyright 2002 Allend Stichter <allen.stichter@idt.com> 5 * Copyright 2008 Florian Fainelli <florian@openwrt.org> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 * 12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, write to the Free Software Foundation, Inc., 25 * 675 Mass Ave, Cambridge, MA 02139, USA. 26 * 27 */ 28 29 #ifndef __ASM_RC32434_ETH_H 30 #define __ASM_RC32434_ETH_H 31 32 33 #define ETH0_BASE_ADDR 0x18060000 34 35 struct eth_regs { 36 u32 ethintfc; 37 u32 ethfifott; 38 u32 etharc; 39 u32 ethhash0; 40 u32 ethhash1; 41 u32 ethu0[4]; /* Reserved. */ 42 u32 ethpfs; 43 u32 ethmcp; 44 u32 eth_u1[10]; /* Reserved. */ 45 u32 ethspare; 46 u32 eth_u2[42]; /* Reserved. */ 47 u32 ethsal0; 48 u32 ethsah0; 49 u32 ethsal1; 50 u32 ethsah1; 51 u32 ethsal2; 52 u32 ethsah2; 53 u32 ethsal3; 54 u32 ethsah3; 55 u32 ethrbc; 56 u32 ethrpc; 57 u32 ethrupc; 58 u32 ethrfc; 59 u32 ethtbc; 60 u32 ethgpf; 61 u32 eth_u9[50]; /* Reserved. */ 62 u32 ethmac1; 63 u32 ethmac2; 64 u32 ethipgt; 65 u32 ethipgr; 66 u32 ethclrt; 67 u32 ethmaxf; 68 u32 eth_u10; /* Reserved. */ 69 u32 ethmtest; 70 u32 miimcfg; 71 u32 miimcmd; 72 u32 miimaddr; 73 u32 miimwtd; 74 u32 miimrdd; 75 u32 miimind; 76 u32 eth_u11; /* Reserved. */ 77 u32 eth_u12; /* Reserved. */ 78 u32 ethcfsa0; 79 u32 ethcfsa1; 80 u32 ethcfsa2; 81 }; 82 83 /* Ethernet interrupt registers */ 84 #define ETH_INT_FC_EN (1 << 0) 85 #define ETH_INT_FC_ITS (1 << 1) 86 #define ETH_INT_FC_RIP (1 << 2) 87 #define ETH_INT_FC_JAM (1 << 3) 88 #define ETH_INT_FC_OVR (1 << 4) 89 #define ETH_INT_FC_UND (1 << 5) 90 #define ETH_INT_FC_IOC 0x000000c0 91 92 /* Ethernet FIFO registers */ 93 #define ETH_FIFI_TT_TTH_BIT 0 94 #define ETH_FIFO_TT_TTH 0x0000007f 95 96 /* Ethernet ARC/multicast registers */ 97 #define ETH_ARC_PRO (1 << 0) 98 #define ETH_ARC_AM (1 << 1) 99 #define ETH_ARC_AFM (1 << 2) 100 #define ETH_ARC_AB (1 << 3) 101 102 /* Ethernet SAL registers */ 103 #define ETH_SAL_BYTE_5 0x000000ff 104 #define ETH_SAL_BYTE_4 0x0000ff00 105 #define ETH_SAL_BYTE_3 0x00ff0000 106 #define ETH_SAL_BYTE_2 0xff000000 107 108 /* Ethernet SAH registers */ 109 #define ETH_SAH_BYTE1 0x000000ff 110 #define ETH_SAH_BYTE0 0x0000ff00 111 112 /* Ethernet GPF register */ 113 #define ETH_GPF_PTV 0x0000ffff 114 115 /* Ethernet PFG register */ 116 #define ETH_PFS_PFD (1 << 0) 117 118 /* Ethernet CFSA[0-3] registers */ 119 #define ETH_CFSA0_CFSA4 0x000000ff 120 #define ETH_CFSA0_CFSA5 0x0000ff00 121 #define ETH_CFSA1_CFSA2 0x000000ff 122 #define ETH_CFSA1_CFSA3 0x0000ff00 123 #define ETH_CFSA1_CFSA0 0x000000ff 124 #define ETH_CFSA1_CFSA1 0x0000ff00 125 126 /* Ethernet MAC1 registers */ 127 #define ETH_MAC1_RE (1 << 0) 128 #define ETH_MAC1_PAF (1 << 1) 129 #define ETH_MAC1_RFC (1 << 2) 130 #define ETH_MAC1_TFC (1 << 3) 131 #define ETH_MAC1_LB (1 << 4) 132 #define ETH_MAC1_MR (1 << 31) 133 134 /* Ethernet MAC2 registers */ 135 #define ETH_MAC2_FD (1 << 0) 136 #define ETH_MAC2_FLC (1 << 1) 137 #define ETH_MAC2_HFE (1 << 2) 138 #define ETH_MAC2_DC (1 << 3) 139 #define ETH_MAC2_CEN (1 << 4) 140 #define ETH_MAC2_PE (1 << 5) 141 #define ETH_MAC2_VPE (1 << 6) 142 #define ETH_MAC2_APE (1 << 7) 143 #define ETH_MAC2_PPE (1 << 8) 144 #define ETH_MAC2_LPE (1 << 9) 145 #define ETH_MAC2_NB (1 << 12) 146 #define ETH_MAC2_BP (1 << 13) 147 #define ETH_MAC2_ED (1 << 14) 148 149 /* Ethernet IPGT register */ 150 #define ETH_IPGT 0x0000007f 151 152 /* Ethernet IPGR registers */ 153 #define ETH_IPGR_IPGR2 0x0000007f 154 #define ETH_IPGR_IPGR1 0x00007f00 155 156 /* Ethernet CLRT registers */ 157 #define ETH_CLRT_MAX_RET 0x0000000f 158 #define ETH_CLRT_COL_WIN 0x00003f00 159 160 /* Ethernet MAXF register */ 161 #define ETH_MAXF 0x0000ffff 162 163 /* Ethernet test registers */ 164 #define ETH_TEST_REG (1 << 2) 165 #define ETH_MCP_DIV 0x000000ff 166 167 /* MII registers */ 168 #define ETH_MII_CFG_RSVD 0x0000000c 169 #define ETH_MII_CMD_RD (1 << 0) 170 #define ETH_MII_CMD_SCN (1 << 1) 171 #define ETH_MII_REG_ADDR 0x0000001f 172 #define ETH_MII_PHY_ADDR 0x00001f00 173 #define ETH_MII_WTD_DATA 0x0000ffff 174 #define ETH_MII_RDD_DATA 0x0000ffff 175 #define ETH_MII_IND_BSY (1 << 0) 176 #define ETH_MII_IND_SCN (1 << 1) 177 #define ETH_MII_IND_NV (1 << 2) 178 179 /* 180 * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors. 181 */ 182 183 #define ETH_RX_FD (1 << 0) 184 #define ETH_RX_LD (1 << 1) 185 #define ETH_RX_ROK (1 << 2) 186 #define ETH_RX_FM (1 << 3) 187 #define ETH_RX_MP (1 << 4) 188 #define ETH_RX_BP (1 << 5) 189 #define ETH_RX_VLT (1 << 6) 190 #define ETH_RX_CF (1 << 7) 191 #define ETH_RX_OVR (1 << 8) 192 #define ETH_RX_CRC (1 << 9) 193 #define ETH_RX_CV (1 << 10) 194 #define ETH_RX_DB (1 << 11) 195 #define ETH_RX_LE (1 << 12) 196 #define ETH_RX_LOR (1 << 13) 197 #define ETH_RX_CES (1 << 14) 198 #define ETH_RX_LEN_BIT 16 199 #define ETH_RX_LEN 0xffff0000 200 201 #define ETH_TX_FD (1 << 0) 202 #define ETH_TX_LD (1 << 1) 203 #define ETH_TX_OEN (1 << 2) 204 #define ETH_TX_PEN (1 << 3) 205 #define ETH_TX_CEN (1 << 4) 206 #define ETH_TX_HEN (1 << 5) 207 #define ETH_TX_TOK (1 << 6) 208 #define ETH_TX_MP (1 << 7) 209 #define ETH_TX_BP (1 << 8) 210 #define ETH_TX_UND (1 << 9) 211 #define ETH_TX_OF (1 << 10) 212 #define ETH_TX_ED (1 << 11) 213 #define ETH_TX_EC (1 << 12) 214 #define ETH_TX_LC (1 << 13) 215 #define ETH_TX_TD (1 << 14) 216 #define ETH_TX_CRC (1 << 15) 217 #define ETH_TX_LE (1 << 16) 218 #define ETH_TX_CC 0x001E0000 219 220 #endif /* __ASM_RC32434_ETH_H */ 221