Searched refs:EN0 (Results 1 – 3 of 3) sorted by relevance
298 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + EN0); in ipi_en0_regs_init()300 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + EN0); in ipi_en0_regs_init()302 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + EN0); in ipi_en0_regs_init()304 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + EN0); in ipi_en0_regs_init()306 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + EN0); in ipi_en0_regs_init()308 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + EN0); in ipi_en0_regs_init()310 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + EN0); in ipi_en0_regs_init()312 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + EN0); in ipi_en0_regs_init()314 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + EN0); in ipi_en0_regs_init()316 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + EN0); in ipi_en0_regs_init()[all …]
22 #define EN0 0x04 macro
40 (EN0, EN1), and 3 master sequencing timers called FPS0, FPS1 and FPS2.79 hardware input to PMIC i.e. EN0, EN1 or85 for hardware input pin EN0.