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Searched refs:DppClocks (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_smu.h106 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS]; member
132 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS]; member
H A Ddcn35_clk_mgr.c1085 max_dppclk = find_max_clk_value(clock_table->DppClocks, in dcn35_clk_mgr_helper_populate_bw_params()
1154 find_max_clk_value(clock_table->DppClocks, NUM_DPPCLK_DPM_LEVELS); in dcn35_clk_mgr_helper_populate_bw_params()
1386 smu_dpm_clks_b->dpm_clks->DppClocks[i] = smu_dpm_clks_a->dpm_clks->DppClocks[i]; in translate_to_DpmClocks_t_dcn35()
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu15_driver_if_v15_0_0.h123 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS]; member
152 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS]; member
H A Dsmu13_driver_if_v13_0_5.h113 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS]; member
H A Dsmu13_driver_if_yellow_carp.h124 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS]; member
H A Dsmu13_driver_if_v13_0_4.h125 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS]; member
H A Dsmu11_driver_if_vangogh.h130 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS]; member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_smu.h52 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS]; member
H A Ddcn314_clk_mgr.c656 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled); in dcn314_clk_mgr_helper_populate_bw_params()
718 …bw_params->clk_table.entries[i].dppclk_mhz = find_max_clk_value(clock_table->DppClocks, NUM_DPPCLK… in dcn314_clk_mgr_helper_populate_bw_params()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_smu.h72 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS]; member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_smu.h80 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS]; member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.h101 uint32_t DppClocks[VG_NUM_DPPCLK_DPM_LEVELS]; member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_smu.h133 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS]; member
H A Ddcn31_clk_mgr.c597 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled); in dcn31_clk_mgr_helper_populate_bw_params()