Searched refs:DWORDS (Results 1 – 5 of 5) sorted by relevance
92 actual raw RC5 code will span 2-3 DWORDS, depending on the actual alignment.
1442 Write and Invalidate Command at a not cache-line-aligned 4 DWORDS boundary.1443 This is only possible when Cache Line Size is 8 DWORDS or greater.1444 Pentium systems use a 8 DWORDS cache line size and so are concerned by1445 this chip bug, unlike i486 systems that use a 4 DWORDS cache line size.1459 The only driver internal data structure that is greater than 8 DWORDS and1461 the context of the SCSI transfer. This data structure is aligned on 8 DWORDS1466 performed using a buffer that is 4 DWORDS but not cache-line aligned.2149 As a consequence, PCI devices generally expect DWORDS using little endian
210 - Cache line size set to 16 DWORDS for Sparc (from DSM).484 . Programmed burst length set to 64 DWORDS (instead of 128).485 (Note: SYMBIOS uses 32 DWORDS for the SDMS BIOS)
466 by reading DWORDS at a time instead of BYTES.
460 DWORDS = 0x3F, enumerator