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Searched refs:DSCEnable (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_mode_vba_util_32.h224 bool DSCEnable,
267 bool DSCEnable,
297 bool DSCEnable,
310 bool DSCEnable,
H A Ddisplay_mode_vba_32.c2105 mode_lib->vba.DSCEnable[k], in dml32_ModeSupportAndSystemConfigurationFull()
2361 if (mode_lib->vba.DSCEnable[k] && mode_lib->vba.ForcedOutputLinkBPP[k] != 0) in dml32_ModeSupportAndSystemConfigurationFull()
2363 if (mode_lib->vba.DSCEnable[k] && mode_lib->vba.OutputFormat[k] == dm_n422 in dml32_ModeSupportAndSystemConfigurationFull()
/linux/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml2_utils.c125 dml_output_array->DSCEnable[dst_index] = dml_output_array->DSCEnable[src_index]; in dml2_util_copy_dml_output()
H A Ddisplay_mode_core_structs.h571 …enum dml_dsc_enable DSCEnable[__DML_NUM_PLANES__]; //< brief for mode support check; use to determ… member
H A Ddml2_translation_helper.c740 out->DSCEnable[location] = (enum dml_dsc_enable)in->timing.flags.DSC; in populate_dml_output_cfg_from_stream_state()
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
H A Ddml2_core_shared.c123 bool DSCEnable,
376 bool DSCEnable,
405 enum dml2_dsc_enable_option DSCEnable,
428 bool DSCEnable,
3964 bool DSCEnable, in TruncToValidBPP() argument
4017 } else if (DSCEnable && Output == dml2_dp) { in TruncToValidBPP()
4023 ODMMode = DSCEnable ? ODMModeDSC : ODMModeNoDSC; in TruncToValidBPP()
4030 if (DSCEnable) { in TruncToValidBPP()
4050 …if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 || DesiredBPP == NonDSCBPP1 || DesiredBPP =… in TruncToValidBPP()
4051 (DSCEnable && DesiredBPP >= MinDSCBPP && DesiredBPP <= MaxDSCBPP))) { in TruncToValidBPP()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddisplay_mode_vba_31.c3587 bool DSCEnable, argument
3630 if (DSCEnable && Output == dm_dp) {
3643 if (DSCEnable) {
3663 …if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 || DesiredBPP == NonDSCBPP1 || DesiredBPP <…
3664 || (DSCEnable && DesiredBPP >= MinDSCBPP && DesiredBPP <= MaxDSCBPP))) {
4309 if (v->DSCEnable[k] == true) {
4346 v->DSCEnable[k] == true && v->ForcedOutputLinkBPP[k] == 0) {
4388 v->DSCEnable[k] == true && v->ForcedOutputLinkBPP[k] == 0) {
4429 if (v->Outbpp == BPP_INVALID && v->DSCEnable[k] == true &&
4544 if (v->DSCEnable[k] == true && v->OutputFormat[k] == dm_n422
/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_vba.h1072 bool DSCEnable[DC__NUM_DPP__MAX]; member
H A Ddisplay_mode_vba.c648 mode_lib->vba.DSCEnable[mode_lib->vba.NumberOfActivePlanes] = dout->dsc_enable; in fetch_pipe_params()