| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | display_mode_vba_util_32.h | 224 bool DSCEnable,
267 bool DSCEnable,
297 bool DSCEnable,
310 bool DSCEnable,
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| H A D | display_mode_vba_32.c | 2110 mode_lib->vba.DSCEnable[k], in dml32_ModeSupportAndSystemConfigurationFull()
2370 if (mode_lib->vba.DSCEnable[k] && mode_lib->vba.ForcedOutputLinkBPP[k] != 0) in dml32_ModeSupportAndSystemConfigurationFull()
2372 if (mode_lib->vba.DSCEnable[k] && mode_lib->vba.OutputFormat[k] == dm_n422 in dml32_ModeSupportAndSystemConfigurationFull()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_utils.c | 125 dml_output_array->DSCEnable[dst_index] = dml_output_array->DSCEnable[src_index]; in dml2_util_copy_dml_output()
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| H A D | display_mode_core.c | 94 enum dml_dsc_enable DSCEnable,
114 dml_bool_t DSCEnable,
383 dml_bool_t DSCEnable,
445 dml_bool_t DSCEnable,
2726 dml_bool_t DSCEnable, in TruncToValidBPP()
2758 hdmifrlparams.compressed = DSCEnable; in TruncToValidBPP()
2807 } else if (DSCEnable && Output == dml_dp) { in TruncToValidBPP()
2813 if (DSCEnable) { in TruncToValidBPP()
2834 if (DSCEnable) { in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
2854 if (!((DSCEnable in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
2724 TruncToValidBPP(dml_float_t LinkBitRate,dml_uint_t Lanes,dml_uint_t HTotal,dml_uint_t HActive,dml_float_t PixelClock,dml_float_t DesiredBPP,dml_bool_t DSCEnable,enum dml_output_encoder_class Output,enum dml_output_format_class Format,dml_uint_t DSCInputBitPerComponent,dml_uint_t DSCSlices,dml_uint_t AudioRate,dml_uint_t AudioLayout,enum dml_odm_mode ODMModeNoDSC,enum dml_odm_mode ODMModeDSC,dml_uint_t * RequiredSlots) TruncToValidBPP() argument
4592 RequiredDTBCLK(dml_bool_t DSCEnable,dml_float_t PixelClock,enum dml_output_format_class OutputFormat,dml_float_t OutputBpp,dml_uint_t DSCSlices,dml_uint_t HTotal,dml_uint_t HActive,dml_uint_t AudioRate,dml_uint_t AudioLayout) RequiredDTBCLK() argument
5376 CalculateOutputLink(dml_float_t PHYCLKPerState,dml_float_t PHYCLKD18PerState,dml_float_t PHYCLKD32PerState,dml_float_t Downspreading,dml_bool_t IsMainSurfaceUsingTheIndicatedTiming,enum dml_output_encoder_class Output,enum dml_output_format_class OutputFormat,dml_uint_t HTotal,dml_uint_t HActive,dml_float_t PixelClockBackEnd,dml_float_t ForcedOutputLinkBPP,dml_uint_t DSCInputBitPerComponent,dml_uint_t NumberOfDSCSlices,dml_float_t AudioSampleRate,dml_uint_t AudioSampleLayout,enum dml_odm_mode ODMModeNoDSC,enum dml_odm_mode ODMModeDSC,enum dml_dsc_enable DSCEnable,dml_uint_t OutputLinkDPLanes,enum dml_output_link_dp_rate OutputLinkDPRate,dml_bool_t * RequiresDSC,dml_bool_t * RequiresFEC,dml_float_t * OutBpp,enum dml_output_type_and_rate__type * OutputType,enum dml_output_type_and_rate__rate * OutputRate,dml_uint_t * RequiredSlots) CalculateOutputLink() argument
5532 CalculateODMMode(dml_uint_t MaximumPixelsPerLinePerDSCUnit,dml_uint_t HActive,enum dml_output_encoder_class Output,enum dml_output_format_class OutputFormat,enum dml_odm_use_policy ODMUse,dml_float_t StateDispclk,dml_float_t MaxDispclk,dml_bool_t DSCEnable,dml_uint_t TotalNumberOfActiveDPP,dml_uint_t MaxNumDPP,dml_float_t PixelClock,dml_float_t DISPCLKDPPCLKDSCCLKDownSpreading,dml_float_t DISPCLKRampingMargin,dml_float_t DISPCLKDPPCLKVCOSpeed,dml_uint_t NumberOfDSCSlices,dml_bool_t * TotalAvailablePipesSupport,dml_uint_t * NumberOfDPP,enum dml_odm_mode * ODMMode,dml_float_t * RequiredDISPCLKPerSurface) CalculateODMMode() argument
[all...] |
| H A D | display_mode_core_structs.h | 627 …enum dml_dsc_enable DSCEnable[__DML_NUM_PLANES__]; //< brief for mode support check; use to determ… member
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| H A D | dml2_translation_helper.c | 791 out->DSCEnable[location] = (enum dml_dsc_enable)in->timing.flags.DSC; in populate_dml_output_cfg_from_stream_state()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/ |
| H A D | dml2_core_dcn4_calcs.c | 1275 bool DSCEnable, in TruncToValidBPP()
1308 l->hdmifrlparams.compressed = DSCEnable; in TruncToValidBPP()
1356 } else if (DSCEnable && Output == dml2_dp) { in TruncToValidBPP()
1362 ODMMode = DSCEnable ? ODMModeDSC : ODMModeNoDSC; in TruncToValidBPP()
1369 if (DSCEnable) { in TruncToValidBPP()
1389 if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 || DesiredBPP == NonDSCBPP1 || DesiredBPP == NonDSCBPP0)) || in dscceComputeDelay()
1390 (DSCEnable && DesiredBPP >= MinDSCBPP && DesiredBPP <= MaxDSCBPP))) { in dscceComputeDelay()
4155 bool DSCEnable, in CalculateODMMode()
4179 bool UseDSC = DSCEnable && (NumberOfDSCSlices > 0); in CalculateODMMode()
4190 DML_LOG_VERBOSE("DML::%s: DSCEnable in CalculateODMMode()
1274 TruncToValidBPP(struct dml2_core_shared_TruncToValidBPP_locals * l,double LinkBitRate,unsigned int Lanes,unsigned int HTotal,unsigned int HActive,double PixelClock,double DesiredBPP,bool DSCEnable,enum dml2_output_encoder_class Output,enum dml2_output_format_class Format,unsigned int DSCInputBitPerComponent,unsigned int DSCSlices,unsigned int AudioRate,unsigned int AudioLayout,enum dml2_odm_mode ODMModeNoDSC,enum dml2_odm_mode ODMModeDSC,unsigned int * RequiredSlots) TruncToValidBPP() argument
4128 CalculateODMMode(unsigned int MaximumPixelsPerLinePerDSCUnit,unsigned int HActive,enum dml2_output_format_class OutFormat,enum dml2_output_encoder_class Output,enum dml2_odm_mode ODMUse,double MaxDispclk,bool DSCEnable,unsigned int TotalNumberOfActiveDPP,unsigned int TotalNumberOfActiveOPP,unsigned int MaxNumDPP,unsigned int MaxNumOPP,double PixelClock,unsigned int NumberOfDSCSlices,bool * TotalAvailablePipesSupport,unsigned int * NumberOfDPP,enum dml2_odm_mode * ODMMode,double * RequiredDISPCLKPerSurface) CalculateODMMode() argument
4241 CalculateOutputLink(struct dml2_core_internal_scratch * s,double PHYCLK,double PHYCLKD18,double PHYCLKD32,double Downspreading,enum dml2_output_encoder_class Output,enum dml2_output_format_class OutputFormat,unsigned int HTotal,unsigned int HActive,double PixelClockBackEnd,double ForcedOutputLinkBPP,unsigned int DSCInputBitPerComponent,unsigned int NumberOfDSCSlices,double AudioSampleRate,unsigned int AudioSampleLayout,enum dml2_odm_mode ODMModeNoDSC,enum dml2_odm_mode ODMModeDSC,enum dml2_dsc_enable_option DSCEnable,unsigned int OutputLinkDPLanes,enum dml2_output_link_dp_rate OutputLinkDPRate,bool * RequiresDSC,bool * RequiresFEC,double * OutBpp,enum dml2_core_internal_output_type * OutputType,enum dml2_core_internal_output_type_rate * OutputRate,unsigned int * RequiredSlots) CalculateOutputLink() argument
4487 RequiredDTBCLK(bool DSCEnable,double PixelClock,enum dml2_output_format_class OutputFormat,double OutputBpp,unsigned int DSCSlices,unsigned int HTotal,unsigned int HActive,unsigned int AudioRate,unsigned int AudioLayout) RequiredDTBCLK() argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_vba.h | 1072 bool DSCEnable[DC__NUM_DPP__MAX]; member
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| H A D | display_mode_vba.c | 648 mode_lib->vba.DSCEnable[mode_lib->vba.NumberOfActivePlanes] = dout->dsc_enable; in fetch_pipe_params()
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