Searched refs:DSCC_CONFIG0 (Results 1 – 6 of 6) sorted by relevance
| /linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/ |
| H A D | dcn401_dsc.c | 246 REG_SET_3(DSCC_CONFIG0, 0, in dsc_write_to_registers()
251 REG_SET_4(DSCC_CONFIG0, 0, ICH_RESET_AT_END_OF_LINE, in dsc_write_to_registers()
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| H A D | dcn401_dsc.h | 205 uint32_t DSCC_CONFIG0; member
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| /linux/drivers/gpu/drm/amd/display/dc/dsc/dcn20/ |
| H A D | dcn20_dsc.h | 37 SRI(DSCC_CONFIG0, DSCC, id),\
464 uint32_t DSCC_CONFIG0; member
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| H A D | dcn20_dsc.c | 606 REG_SET_3(DSCC_CONFIG0, 0, in dsc_write_to_registers()
611 REG_SET_4(DSCC_CONFIG0, 0, ICH_RESET_AT_END_OF_LINE, in dsc_write_to_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| H A D | dcn401_resource.h | 419 SRI_ARR(DSCC_CONFIG0, DSCC, id), SRI_ARR(DSCC_CONFIG1, DSCC, id), \
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.h | 723 SRI_ARR(DSCC_CONFIG0, DSCC, id), SRI_ARR(DSCC_CONFIG1, DSCC, id), \
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