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Searched refs:DRRDisplay (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_mode_vba_util_32.h591 bool DRRDisplay[],
684 bool DRRDisplay,
H A Ddisplay_mode_vba_32.c760 mode_lib->vba.DRRDisplay[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3071 mode_lib->vba.DRRDisplay, in dml32_ModeSupportAndSystemConfigurationFull()
3277 mode_lib->vba.DRRDisplay[k], in dml32_ModeSupportAndSystemConfigurationFull()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_utils.c46 dml_timing_array->DRRDisplay[dst_index] = dml_timing_array->DRRDisplay[src_index]; in dml2_util_copy_dml_timing()
H A Ddisplay_mode_core_structs.h613 dml_bool_t DRRDisplay[__DML_NUM_PLANES__]; member
1273 dml_bool_t *DRRDisplay; member
1340 dml_bool_t *DRRDisplay; member
H A Ddisplay_mode_core.c282 dml_bool_t DRRDisplay,
1746 dml_bool_t DRRDisplay, in CalculateTWait()
1756 !(UseMALLForPStateChange == dml_use_mall_pstate_change_phantom_pipe) && !(SynchronizeDRRDisplaysForUCLKPStateChangeFinal && DRRDisplay)) { in CalculateTWait()
3026 (p->SynchronizeDRRDisplaysForUCLKPStateChangeFinal && (p->DRRDisplay[i] || p->DRRDisplay[j]))) { in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
3040 s->FCLKChangeSupportNumber = ((p->SynchronizeDRRDisplaysForUCLKPStateChangeFinal && p->DRRDisplay[k]) ? 2 : 1); in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
3042 } else if (((s->FCLKChangeSupportNumber == 1) && (p->DRRDisplay[k] || (!s->SynchronizedSurfaces[s->LastSurfaceWithoutMargin][k]))) || (s->FCLKChangeSupportNumber == 2)) in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
3071 s->DRAMClockChangeSupportNumber = (p->SynchronizeDRRDisplaysForUCLKPStateChangeFinal && p->DRRDisplay[k]) ? 2 : 1; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
3073 } else if (((s->DRAMClockChangeSupportNumber == 1) && (p->DRRDisplay[k] || !s->SynchronizedSurfaces[s->LastSurfaceWithoutMargin][k])) || (s->DRAMClockChangeSupportNumber == 2)) { in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
4683 p->DRRDisplay[ in UseMinimumDCFCLK()
1744 CalculateTWait(dml_uint_t PrefetchMode,enum dml_use_mall_for_pstate_change_mode UseMALLForPStateChange,dml_bool_t SynchronizeDRRDisplaysForUCLKPStateChangeFinal,dml_bool_t DRRDisplay,dml_float_t DRAMClockChangeLatency,dml_float_t FCLKChangeLatency,dml_float_t UrgentLatency,dml_float_t SREnterPlusExitTime) CalculateTWait() argument
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H A Ddisplay_mode_util.c550 dml_print("DML: timing_cfg: plane=%d, DRRDisplay = %d\n", i, timing->DRRDisplay[i]);
H A Ddml2_translation_helper.c782 out->DRRDisplay[location] = false; in populate_dml_timing_cfg_from_stream_state()
/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_vba.h452 bool DRRDisplay[DC__NUM_DPP__MAX]; member
H A Ddisplay_mode_vba.c708 mode_lib->vba.DRRDisplay[mode_lib->vba.NumberOfActiveSurfaces] = dst->drr_display; in fetch_pipe_params()