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Searched refs:DRAM_PHYS_BASE (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/accel/habanalabs/include/goya/
H A Dgoya.h24 #define DRAM_PHYS_BASE 0x0ull macro
/linux/drivers/accel/habanalabs/include/gaudi/
H A Dgaudi.h32 #define DRAM_PHYS_BASE 0x0ull macro
/linux/drivers/accel/habanalabs/include/gaudi2/
H A Dgaudi2.h43 #define DRAM_PHYS_BASE 0x1001000000000000ull macro
/linux/drivers/accel/habanalabs/gaudi/
H A DgaudiP.h121 #define CPU_FW_IMAGE_ADDR DRAM_PHYS_BASE
H A Dgaudi.c597 prop->dram_base_address = DRAM_PHYS_BASE; in gaudi_set_fixed_properties()
783 inbound_region.addr = DRAM_PHYS_BASE; in gaudi_init_iatu()
1832 region->region_base = DRAM_PHYS_BASE; in gaudi_set_pci_memory_regions()
3927 gaudi->hbm_bar_cur_addr = DRAM_PHYS_BASE; in gaudi_hw_init()
3933 if (gaudi_set_hbm_bar_base(hdev, DRAM_PHYS_BASE) == U64_MAX) { in gaudi_hw_init()
H A Dgaudi_security.c12934 u32 dram_addr_lo = lower_32_bits(DRAM_PHYS_BASE); in gaudi_init_range_registers_hbw()
12935 u32 dram_addr_hi = upper_32_bits(DRAM_PHYS_BASE); in gaudi_init_range_registers_hbw()
/linux/drivers/accel/habanalabs/goya/
H A DgoyaP.h71 #define CPU_FW_IMAGE_ADDR DRAM_PHYS_BASE
H A Dgoya.c398 prop->dram_base_address = DRAM_PHYS_BASE; in goya_set_fixed_properties()
578 inbound_region.addr = DRAM_PHYS_BASE; in goya_init_iatu()
953 region->region_base = DRAM_PHYS_BASE; in goya_set_pci_memory_regions()
978 goya->ddr_bar_cur_addr = DRAM_PHYS_BASE; in goya_sw_init()
2614 if (goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE) == U64_MAX) { in goya_init_cpu()
2807 goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE); in goya_hw_fini()
H A Dgoya_security.c2384 u32 dram_addr_lo = lower_32_bits(DRAM_PHYS_BASE); in goya_init_security()
2385 u32 dram_addr_hi = upper_32_bits(DRAM_PHYS_BASE); in goya_init_security()
/linux/drivers/accel/habanalabs/gaudi2/
H A Dgaudi2P.h110 #define CPU_FW_IMAGE_ADDR DRAM_PHYS_BASE
H A Dgaudi2.c2347 prop->dram_base_address = DRAM_PHYS_BASE; in gaudi2_set_dram_properties()
2351 prop->dram_user_base_address = DRAM_PHYS_BASE + prop->dram_page_size; in gaudi2_set_dram_properties()
2391 prop->mmu_pgt_addr = DRAM_PHYS_BASE + hbm_drv_base_offset + in gaudi2_set_dram_properties()
2708 inbound_region.addr = DRAM_PHYS_BASE; in gaudi2_init_iatu()
3508 region->region_base = DRAM_PHYS_BASE; in gaudi2_set_pci_memory_regions()
6147 gaudi2->dram_bar_cur_addr = DRAM_PHYS_BASE; in gaudi2_hw_init()
6153 if (gaudi2_set_hbm_bar_base(hdev, DRAM_PHYS_BASE) == U64_MAX) { in gaudi2_hw_init()
11164 if (hl_mem_area_inside_range(raw_addr, sizeof(raw_addr), DRAM_PHYS_BASE, in gaudi2_mmu_scramble_addr()
11184 if (hl_mem_area_inside_range(scrambled_addr, sizeof(scrambled_addr), DRAM_PHYS_BASE, in gaudi2_mmu_descramble_addr()
H A Dgaudi2_security.c3181 rr_cfg.min = hdev->asic_funcs->scramble_addr(hdev, DRAM_PHYS_BASE); in gaudi2_init_mmu_range_registers()