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Searched refs:DP_VID_STREAM_CNTL (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_link_encoder.h69 SRI(DP_VID_STREAM_CNTL, DP, id), \
102 SRI(DP_VID_STREAM_CNTL, DP, id), \
179 uint32_t DP_VID_STREAM_CNTL; member
H A Ddce_stream_encoder.c915 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1); in dce110_stream_encoder_dp_blank()
921 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2); in dce110_stream_encoder_dp_blank()
929 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); in dce110_stream_encoder_dp_blank()
936 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, in dce110_stream_encoder_dp_blank()
1010 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); in dce110_stream_encoder_dp_unblank()
H A Ddce_stream_encoder.h91 SRI(DP_VID_STREAM_CNTL, DP, id), \
162 SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
163 SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
164 SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\
663 uint32_t DP_VID_STREAM_CNTL; member
H A Ddce_link_encoder.c457 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); in set_dp_phy_pattern_hbr2_compliance_cp2520_2()
509 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); in dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2()
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn32/
H A Ddcn32_dio_stream_encoder.c298 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false); in enc32_stream_encoder_dp_unblank()
299 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000); in enc32_stream_encoder_dp_unblank()
344 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); in enc32_stream_encoder_dp_unblank()
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn35/
H A Ddcn35_dio_stream_encoder.c330 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false); in enc35_stream_encoder_dp_unblank()
331 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000); in enc35_stream_encoder_dp_unblank()
356 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); in enc35_stream_encoder_dp_unblank()
H A Ddcn35_dio_stream_encoder.h94 SRI(DP_VID_STREAM_CNTL, DP, id), \
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn314/
H A Ddcn314_dio_stream_encoder.c341 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false); in enc314_stream_encoder_dp_unblank()
342 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000); in enc314_stream_encoder_dp_unblank()
367 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); in enc314_stream_encoder_dp_unblank()
H A Ddcn314_dio_stream_encoder.h96 SRI(DP_VID_STREAM_CNTL, DP, id), \
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn401/
H A Ddcn401_dio_stream_encoder.c323 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false); in enc401_stream_encoder_dp_unblank()
324 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000); in enc401_stream_encoder_dp_unblank()
338 REG_UPDATE_2(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 1, DP_VID_STREAM_DIS_DEFER, 2); in enc401_stream_encoder_dp_unblank()
371 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); in enc401_stream_encoder_dp_unblank()
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn20/
H A Ddcn20_stream_encoder.c515 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false); in enc2_stream_encoder_dp_unblank()
516 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000); in enc2_stream_encoder_dp_unblank()
547 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); in enc2_stream_encoder_dp_unblank()
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn10/
H A Ddcn10_stream_encoder.c919 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1); in enc1_stream_encoder_dp_blank()
926 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2); in enc1_stream_encoder_dp_blank()
934 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); in enc1_stream_encoder_dp_blank()
943 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, in enc1_stream_encoder_dp_blank()
1026 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); in enc1_stream_encoder_dp_unblank()
H A Ddcn10_link_encoder.h62 SRI(DP_VID_STREAM_CNTL, DP, id), \
104 uint32_t DP_VID_STREAM_CNTL; member
H A Ddcn10_stream_encoder.h93 SRI(DP_VID_STREAM_CNTL, DP, id), \
142 uint32_t DP_VID_STREAM_CNTL; member
H A Ddcn10_link_encoder.c389 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); in set_dp_phy_pattern_hbr2_compliance_cp2520_2()
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn30/
H A Ddcn30_dio_link_encoder.h51 SRI(DP_VID_STREAM_CNTL, DP, id), \
H A Ddcn30_dio_stream_encoder.h95 SRI(DP_VID_STREAM_CNTL, DP, id), \
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn301/
H A Ddcn301_dio_link_encoder.h52 SRI(DP_VID_STREAM_CNTL, DP, id), \
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.h126 SRI_ARR(DP_VID_STREAM_CNTL, DP, id), \
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.h294 SRI_ARR(DP_VID_N, DP, id), SRI_ARR(DP_VID_STREAM_CNTL, DP, id), \
330 SRI_ARR(DP_SEC_CNTL, DP, id), SRI_ARR(DP_VID_STREAM_CNTL, DP, id), \
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.h209 SRI_ARR(DP_VID_N, DP, id), SRI_ARR(DP_VID_STREAM_CNTL, DP, id), \