| /linux/include/drm/display/ |
| H A D | drm_dp_helper.h | 48 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
50 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
54 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
57 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
135 bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
136 bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
141 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_link_rate() argument
147 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_lane_count() argument
153 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_enhanced_frame_cap() argument
160 drm_dp_post_lt_adj_req_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_post_lt_adj_req_supported() argument
[all …]
|
| H A D | drm_dp.h | 1691 #define DP_RECEIVER_CAP_SIZE 0xf macro
|
| /linux/drivers/gpu/drm/msm/dp/ |
| H A D | dp_panel.h | 32 u8 dpcd[DP_RECEIVER_CAP_SIZE];
|
| /linux/drivers/gpu/drm/nouveau/include/nvif/ |
| H A D | outp.h | 107 int nvif_outp_dp_train(struct nvif_outp *, u8 dpcd[DP_RECEIVER_CAP_SIZE],
|
| H A D | if0012.h | 243 __u8 dpcd[DP_RECEIVER_CAP_SIZE];
|
| /linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| H A D | outp.h | 48 u8 dpcd[DP_RECEIVER_CAP_SIZE];
|
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_mode.h | 554 u8 dpcd[DP_RECEIVER_CAP_SIZE];
|
| /linux/drivers/gpu/drm/nouveau/nvif/ |
| H A D | outp.c | 113 nvif_outp_dp_train(struct nvif_outp *outp, u8 dpcd[DP_RECEIVER_CAP_SIZE], u8 lttprs, in nvif_outp_dp_train() argument
|
| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_dp_tunnel.c | 302 u8 dpcd[DP_RECEIVER_CAP_SIZE]; in intel_dp_tunnel_resume()
|
| H A D | intel_dp_mst.c | 1618 u8 dpcd_caps[DP_RECEIVER_CAP_SIZE]; in intel_dp_mst_read_decompression_port_dsc_caps()
1641 u8 dpcd[DP_RECEIVER_CAP_SIZE]; in detect_dsc_hblank_expansion_quirk()
|
| H A D | intel_display_types.h | 1797 u8 dpcd[DP_RECEIVER_CAP_SIZE];
|
| H A D | intel_dp.c | 6578 u8 dpcd[DP_RECEIVER_CAP_SIZE]; in intel_dp_hpd_pulse()
|
| /linux/drivers/gpu/drm/bridge/cadence/ |
| H A D | cdns-mhdp8546-core.c | 1331 u8 dpcd[DP_RECEIVER_CAP_SIZE]) in cdns_mhdp_fill_sink_caps() argument
1356 u8 dpcd[DP_RECEIVER_CAP_SIZE], amp[2]; in cdns_mhdp_link_up()
1372 err = drm_dp_dpcd_read(&mhdp->aux, addr, dpcd, DP_RECEIVER_CAP_SIZE); in cdns_mhdp_link_up()
|
| /linux/drivers/gpu/drm/bridge/ |
| H A D | tc358767.c | 359 u8 dpcd[DP_RECEIVER_CAP_SIZE];
844 DP_RECEIVER_CAP_SIZE); in tc_get_display_props()
|
| /linux/drivers/gpu/drm/display/ |
| H A D | drm_dp_mst_topology.c | 3616 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_read_mst_cap() argument
4970 seq_printf(m, "dpcd: %*ph\n", DP_RECEIVER_CAP_SIZE, buf); in drm_dp_mst_dump_topology()
6156 u8 dpcd_ext[DP_RECEIVER_CAP_SIZE]; in drm_dp_mst_dsc_aux_for_port()
|
| /linux/drivers/gpu/drm/xlnx/ |
| H A D | zynqmp_dp.c | 406 u8 dpcd[DP_RECEIVER_CAP_SIZE];
|
| /linux/drivers/gpu/drm/bridge/synopsys/ |
| H A D | dw-dp.c | 279 u8 dpcd[DP_RECEIVER_CAP_SIZE];
|
| /linux/drivers/gpu/drm/mediatek/ |
| H A D | mtk_dp.c | 107 u8 rx_cap[DP_RECEIVER_CAP_SIZE];
|