Searched refs:DP_MAX_LANE_COUNT (Results 1 – 9 of 9) sorted by relevance
148 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; in drm_dp_max_lane_count()155 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); in drm_dp_enhanced_frame_cap()169 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED; in drm_dp_tps3_supported()
116 #define DP_MAX_LANE_COUNT 0x002 macro
103 outp->dp.link_nr = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; in nouveau_dp_probe_dpcd()340 if ( (outp->dp.dpcd[DP_MAX_LANE_COUNT] & 0x20) && in nouveau_dp_train_link()
1294 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0) in dp_overwrite_extended_receiver_cap()1309 DP_MAX_LANE_COUNT - DP_DPCD_REV]; in dp_overwrite_extended_receiver_cap()1744 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0) in retrieve_link_cap()1767 DP_MAX_LANE_COUNT - DP_DPCD_REV]; in retrieve_link_cap()
185 ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data); in analogix_dp_is_enhanced_mode_available()548 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data); in analogix_dp_get_max_rx_lane_count()
743 if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp) in amdgpu_atombios_dp_link_train()
826 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp) in radeon_dp_link_train()
327 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; in cdv_intel_dp_max_lane_count()1076 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { in cdv_intel_dp_mode_set()
1604 bool enhancedFraming = outp->dp.dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP; in nv50_sor_dp_watermark_sst()