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Searched refs:DP_DSC_MODE (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dio/dcn32/
H A Ddcn32_dio_stream_encoder.c361 REG_UPDATE(DP_DSC_CNTL, DP_DSC_MODE, dsc_mode == OPTC_DSC_DISABLED ? 0 : 1); in enc32_dp_set_dsc_config()
372 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); in enc32_read_state()
H A Ddcn32_dio_stream_encoder.h164 SE_SF(DP0_DP_DSC_CNTL, DP_DSC_MODE, mask_sh),\
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn314/
H A Ddcn314_dio_stream_encoder.c399 REG_UPDATE(DP_DSC_CNTL, DP_DSC_MODE, dsc_mode == OPTC_DSC_DISABLED ? 0 : 1); in enc314_dp_set_dsc_config()
410 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); in enc314_read_state()
H A Ddcn314_dio_stream_encoder.h243 SE_SF(DP0_DP_DSC_CNTL, DP_DSC_MODE, mask_sh),\
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn20/
H A Ddcn20_stream_encoder.h70 SE_SF(DP0_DP_DSC_CNTL, DP_DSC_MODE, mask_sh),\
H A Ddcn20_stream_encoder.c288 DP_DSC_MODE, dsc_mode, in enc2_dp_set_dsc_config()
356 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); in enc2_read_state()
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn30/
H A Ddcn30_dio_stream_encoder.c311 DP_DSC_MODE, dsc_mode, in enc3_dp_set_dsc_config()
392 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); in enc3_read_state()
H A Ddcn30_dio_stream_encoder.h258 SE_SF(DP0_DP_DSC_CNTL, DP_DSC_MODE, mask_sh),\
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn35/
H A Ddcn35_dio_stream_encoder.h244 SE_SF(DP0_DP_DSC_CNTL, DP_DSC_MODE, mask_sh),\
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn10/
H A Ddcn10_stream_encoder.h528 type DP_DSC_MODE;\
/linux/drivers/gpu/drm/amd/include/
H A Dnavi10_enum.h6255 typedef enum DP_DSC_MODE { enum
6259 } DP_DSC_MODE; typedef
H A Dsoc21_enum.h6259 typedef enum DP_DSC_MODE { enum
6263 } DP_DSC_MODE; typedef