Home
last modified time | relevance | path

Searched refs:DPU_REG_WRITE (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_util.c173 DPU_REG_WRITE(c, in _dpu_hw_setup_scaler3_lut()
183 DPU_REG_WRITE(c, QSEED3_COEF_LUT_CTRL + offset, BIT(0)); in _dpu_hw_setup_scaler3_lut()
197 DPU_REG_WRITE(c, QSEED3LITE_DIR_FILTER_WEIGHT + offset, scaler3_cfg->dir_weight); in _dpu_hw_setup_scaler3lite_lut()
225 DPU_REG_WRITE(c, in _dpu_hw_setup_scaler3lite_lut()
234 DPU_REG_WRITE(c, QSEED3_COEF_LUT_CTRL + offset, BIT(0)); in _dpu_hw_setup_scaler3lite_lut()
272 DPU_REG_WRITE(c, QSEED3_DE_SHARPEN + offset, sharp_lvl); in _dpu_hw_setup_scaler3_de()
273 DPU_REG_WRITE(c, QSEED3_DE_SHARPEN_CTL + offset, sharp_ctl); in _dpu_hw_setup_scaler3_de()
274 DPU_REG_WRITE(c, QSEED3_DE_SHAPE_CTL + offset, shape_ctl); in _dpu_hw_setup_scaler3_de()
275 DPU_REG_WRITE(c, QSEED3_DE_THRESHOLD + offset, de_thr); in _dpu_hw_setup_scaler3_de()
276 DPU_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_0 + offset, adjust_a); in _dpu_hw_setup_scaler3_de()
[all …]
H A Ddpu_hw_dsc.c42 DPU_REG_WRITE(c, DSC_COMMON_MODE, 0); in dpu_hw_dsc_disable()
57 DPU_REG_WRITE(c, DSC_COMMON_MODE, mode); in dpu_hw_dsc_config()
74 DPU_REG_WRITE(c, DSC_ENC, data); in dpu_hw_dsc_config()
78 DPU_REG_WRITE(c, DSC_PICTURE, data); in dpu_hw_dsc_config()
82 DPU_REG_WRITE(c, DSC_SLICE, data); in dpu_hw_dsc_config()
85 DPU_REG_WRITE(c, DSC_CHUNK_SIZE, data); in dpu_hw_dsc_config()
89 DPU_REG_WRITE(c, DSC_DELAY, data); in dpu_hw_dsc_config()
92 DPU_REG_WRITE(c, DSC_SCALE_INITIAL, data); in dpu_hw_dsc_config()
95 DPU_REG_WRITE(c, DSC_SCALE_DEC_INTERVAL, data); in dpu_hw_dsc_config()
98 DPU_REG_WRITE(c, DSC_SCALE_INC_INTERVAL, data); in dpu_hw_dsc_config()
[all …]
H A Ddpu_hw_wb.c60 DPU_REG_WRITE(c, WB_DST0_ADDR, data->dest.plane_addr[0]); in dpu_hw_wb_setup_outaddress()
61 DPU_REG_WRITE(c, WB_DST1_ADDR, data->dest.plane_addr[1]); in dpu_hw_wb_setup_outaddress()
62 DPU_REG_WRITE(c, WB_DST2_ADDR, data->dest.plane_addr[2]); in dpu_hw_wb_setup_outaddress()
63 DPU_REG_WRITE(c, WB_DST3_ADDR, data->dest.plane_addr[3]); in dpu_hw_wb_setup_outaddress()
115 DPU_REG_WRITE(c, WB_ALPHA_X_VALUE, 0xFF); in dpu_hw_wb_setup_format()
116 DPU_REG_WRITE(c, WB_DST_FORMAT, dst_format); in dpu_hw_wb_setup_format()
117 DPU_REG_WRITE(c, WB_DST_OP_MODE, opmode); in dpu_hw_wb_setup_format()
118 DPU_REG_WRITE(c, WB_DST_PACK_PATTERN, pattern); in dpu_hw_wb_setup_format()
119 DPU_REG_WRITE(c, WB_DST_YSTRIDE0, ystride0); in dpu_hw_wb_setup_format()
120 DPU_REG_WRITE(c, WB_DST_YSTRIDE1, ystride1); in dpu_hw_wb_setup_format()
[all …]
H A Ddpu_hw_top.c64 DPU_REG_WRITE(c, SSPP_SPARE, cfg->split_flush_en ? 0x1 : 0x0); in dpu_hw_setup_split_pipe()
65 DPU_REG_WRITE(c, SPLIT_DISPLAY_LOWER_PIPE_CTRL, lower_pipe); in dpu_hw_setup_split_pipe()
66 DPU_REG_WRITE(c, SPLIT_DISPLAY_UPPER_PIPE_CTRL, upper_pipe); in dpu_hw_setup_split_pipe()
67 DPU_REG_WRITE(c, SPLIT_DISPLAY_EN, cfg->en & 0x1); in dpu_hw_setup_split_pipe()
154 DPU_REG_WRITE(c, wd_load_value, in dpu_hw_setup_wd_timer()
157 DPU_REG_WRITE(c, wd_ctl, BIT(0)); /* clear timer */ in dpu_hw_setup_wd_timer()
161 DPU_REG_WRITE(c, wd_ctl2, reg); in dpu_hw_setup_wd_timer()
190 DPU_REG_WRITE(c, MDP_VSYNC_SEL, reg); in dpu_hw_setup_vsync_sel()
233 DPU_REG_WRITE(c, HDMI_DP_CORE_SELECT, 0x1); in dpu_hw_intf_audio_select()
263 DPU_REG_WRITE(c, MDP_DP_PHY_INTF_SEL, sel); in dpu_hw_dp_phy_intf_sel()
H A Ddpu_hw_cwb.c44 DPU_REG_WRITE(c, CWB_MUX, cwb_mux_cfg); in dpu_hw_cwb_config()
45 DPU_REG_WRITE(c, CWB_MODE, input); in dpu_hw_cwb_config()
H A Ddpu_hw_util.h339 #define DPU_REG_WRITE(c, off, val) dpu_reg_write(c, off, val, #off) macro