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Searched refs:DPG3_DPG_CONTROL__DPG_HRES_MASK (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_1_sh_mask.h22440 #define DPG3_DPG_CONTROL__DPG_HRES_MASK … macro
H A Ddcn_3_2_1_sh_mask.h23870 #define DPG3_DPG_CONTROL__DPG_HRES_MASK … macro
H A Ddcn_2_1_0_sh_mask.h26241 #define DPG3_DPG_CONTROL__DPG_HRES_MASK … macro
H A Ddcn_3_5_1_sh_mask.h20533 #define DPG3_DPG_CONTROL__DPG_HRES_MASK … macro
H A Ddcn_3_5_0_sh_mask.h20554 #define DPG3_DPG_CONTROL__DPG_HRES_MASK … macro
H A Ddcn_3_1_2_sh_mask.h28663 #define DPG3_DPG_CONTROL__DPG_HRES_MASK … macro
H A Ddcn_3_1_5_sh_mask.h26686 #define DPG3_DPG_CONTROL__DPG_HRES_MASK … macro
H A Ddcn_3_1_6_sh_mask.h29427 #define DPG3_DPG_CONTROL__DPG_HRES_MASK … macro
H A Ddcn_3_1_4_sh_mask.h30680 #define DPG3_DPG_CONTROL__DPG_HRES_MASK … macro
H A Ddcn_3_0_2_sh_mask.h25503 #define DPG3_DPG_CONTROL__DPG_HRES_MASK … macro
H A Ddcn_2_0_0_sh_mask.h29590 #define DPG3_DPG_CONTROL__DPG_HRES_MASK … macro
H A Ddcn_3_0_0_sh_mask.h28747 #define DPG3_DPG_CONTROL__DPG_HRES_MASK … macro
H A Ddcn_3_2_0_sh_mask.h23894 #define DPG3_DPG_CONTROL__DPG_HRES_MASK … macro