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Searched refs:DPG2_DPG_CONTROL__DPG_VRES__SHIFT (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_1_sh_mask.h22192 #define DPG2_DPG_CONTROL__DPG_VRES__SHIFT … macro
H A Ddcn_3_2_1_sh_mask.h23622 #define DPG2_DPG_CONTROL__DPG_VRES__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h25989 #define DPG2_DPG_CONTROL__DPG_VRES__SHIFT … macro
H A Ddcn_3_5_1_sh_mask.h20331 #define DPG2_DPG_CONTROL__DPG_VRES__SHIFT … macro
H A Ddcn_3_5_0_sh_mask.h20352 #define DPG2_DPG_CONTROL__DPG_VRES__SHIFT … macro
H A Ddcn_3_1_2_sh_mask.h28415 #define DPG2_DPG_CONTROL__DPG_VRES__SHIFT … macro
H A Ddcn_3_1_5_sh_mask.h26438 #define DPG2_DPG_CONTROL__DPG_VRES__SHIFT … macro
H A Ddcn_3_1_6_sh_mask.h29179 #define DPG2_DPG_CONTROL__DPG_VRES__SHIFT … macro
H A Ddcn_3_1_4_sh_mask.h30432 #define DPG2_DPG_CONTROL__DPG_VRES__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h25255 #define DPG2_DPG_CONTROL__DPG_VRES__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h29338 #define DPG2_DPG_CONTROL__DPG_VRES__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h28502 #define DPG2_DPG_CONTROL__DPG_VRES__SHIFT … macro
H A Ddcn_3_2_0_sh_mask.h23646 #define DPG2_DPG_CONTROL__DPG_VRES__SHIFT … macro