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Searched refs:DPG1_DPG_CONTROL__DPG_VRES_MASK (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_sh_mask.h13999 #define DPG1_DPG_CONTROL__DPG_VRES_MASK … macro
H A Ddcn_3_0_3_sh_mask.h13888 #define DPG1_DPG_CONTROL__DPG_VRES_MASK … macro
H A Ddcn_3_0_1_sh_mask.h21959 #define DPG1_DPG_CONTROL__DPG_VRES_MASK … macro
H A Ddcn_3_2_1_sh_mask.h23389 #define DPG1_DPG_CONTROL__DPG_VRES_MASK … macro
H A Ddcn_2_1_0_sh_mask.h25752 #define DPG1_DPG_CONTROL__DPG_VRES_MASK … macro
H A Ddcn_3_5_1_sh_mask.h20144 #define DPG1_DPG_CONTROL__DPG_VRES_MASK … macro
H A Ddcn_3_5_0_sh_mask.h20165 #define DPG1_DPG_CONTROL__DPG_VRES_MASK … macro
H A Ddcn_3_1_2_sh_mask.h28182 #define DPG1_DPG_CONTROL__DPG_VRES_MASK … macro
H A Ddcn_3_1_5_sh_mask.h26205 #define DPG1_DPG_CONTROL__DPG_VRES_MASK … macro
H A Ddcn_3_1_6_sh_mask.h28946 #define DPG1_DPG_CONTROL__DPG_VRES_MASK … macro
H A Ddcn_3_1_4_sh_mask.h30199 #define DPG1_DPG_CONTROL__DPG_VRES_MASK … macro
H A Ddcn_3_0_2_sh_mask.h25022 #define DPG1_DPG_CONTROL__DPG_VRES_MASK … macro
H A Ddcn_2_0_0_sh_mask.h29101 #define DPG1_DPG_CONTROL__DPG_VRES_MASK … macro
H A Ddcn_3_0_0_sh_mask.h28272 #define DPG1_DPG_CONTROL__DPG_VRES_MASK … macro
H A Ddcn_3_2_0_sh_mask.h23413 #define DPG1_DPG_CONTROL__DPG_VRES_MASK … macro