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Searched refs:DPG1_DPG_CONTROL__DPG_HRES_MASK (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_sh_mask.h14000 #define DPG1_DPG_CONTROL__DPG_HRES_MASK … macro
H A Ddcn_3_0_3_sh_mask.h13889 #define DPG1_DPG_CONTROL__DPG_HRES_MASK … macro
H A Ddcn_3_0_1_sh_mask.h21960 #define DPG1_DPG_CONTROL__DPG_HRES_MASK … macro
H A Ddcn_3_2_1_sh_mask.h23390 #define DPG1_DPG_CONTROL__DPG_HRES_MASK … macro
H A Ddcn_2_1_0_sh_mask.h25753 #define DPG1_DPG_CONTROL__DPG_HRES_MASK … macro
H A Ddcn_3_5_1_sh_mask.h20145 #define DPG1_DPG_CONTROL__DPG_HRES_MASK … macro
H A Ddcn_3_5_0_sh_mask.h20166 #define DPG1_DPG_CONTROL__DPG_HRES_MASK … macro
H A Ddcn_3_1_2_sh_mask.h28183 #define DPG1_DPG_CONTROL__DPG_HRES_MASK … macro
H A Ddcn_3_1_5_sh_mask.h26206 #define DPG1_DPG_CONTROL__DPG_HRES_MASK … macro
H A Ddcn_3_1_6_sh_mask.h28947 #define DPG1_DPG_CONTROL__DPG_HRES_MASK … macro
H A Ddcn_3_1_4_sh_mask.h30200 #define DPG1_DPG_CONTROL__DPG_HRES_MASK … macro
H A Ddcn_3_0_2_sh_mask.h25023 #define DPG1_DPG_CONTROL__DPG_HRES_MASK … macro
H A Ddcn_2_0_0_sh_mask.h29102 #define DPG1_DPG_CONTROL__DPG_HRES_MASK … macro
H A Ddcn_3_0_0_sh_mask.h28273 #define DPG1_DPG_CONTROL__DPG_HRES_MASK … macro
H A Ddcn_3_2_0_sh_mask.h23414 #define DPG1_DPG_CONTROL__DPG_HRES_MASK … macro