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Searched refs:DPG0_DPG_CONTROL__DPG_VRES__SHIFT (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_sh_mask.h13793 #define DPG0_DPG_CONTROL__DPG_VRES__SHIFT … macro
H A Ddcn_3_0_3_sh_mask.h13641 #define DPG0_DPG_CONTROL__DPG_VRES__SHIFT … macro
H A Ddcn_3_0_1_sh_mask.h21712 #define DPG0_DPG_CONTROL__DPG_VRES__SHIFT … macro
H A Ddcn_3_2_1_sh_mask.h23142 #define DPG0_DPG_CONTROL__DPG_VRES__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h25501 #define DPG0_DPG_CONTROL__DPG_VRES__SHIFT … macro
H A Ddcn_3_5_1_sh_mask.h19943 #define DPG0_DPG_CONTROL__DPG_VRES__SHIFT … macro
H A Ddcn_3_5_0_sh_mask.h19964 #define DPG0_DPG_CONTROL__DPG_VRES__SHIFT … macro
H A Ddcn_3_1_2_sh_mask.h27935 #define DPG0_DPG_CONTROL__DPG_VRES__SHIFT … macro
H A Ddcn_3_1_5_sh_mask.h25958 #define DPG0_DPG_CONTROL__DPG_VRES__SHIFT … macro
H A Ddcn_3_1_6_sh_mask.h28699 #define DPG0_DPG_CONTROL__DPG_VRES__SHIFT … macro
H A Ddcn_3_1_4_sh_mask.h29952 #define DPG0_DPG_CONTROL__DPG_VRES__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h24775 #define DPG0_DPG_CONTROL__DPG_VRES__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h28850 #define DPG0_DPG_CONTROL__DPG_VRES__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h28028 #define DPG0_DPG_CONTROL__DPG_VRES__SHIFT … macro
H A Ddcn_3_2_0_sh_mask.h23166 #define DPG0_DPG_CONTROL__DPG_VRES__SHIFT … macro