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Searched refs:DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h21089 #define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT … macro
H A Ddcn_3_0_1_sh_mask.h32227 #define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT … macro
H A Ddcn_3_2_1_sh_mask.h30195 #define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT … macro
H A Ddcn_3_5_1_sh_mask.h29604 #define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT … macro
H A Ddcn_3_5_0_sh_mask.h29625 #define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT … macro
H A Ddcn_3_1_2_sh_mask.h35173 #define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT … macro
H A Ddcn_3_1_5_sh_mask.h33137 #define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT … macro
H A Ddcn_3_1_6_sh_mask.h36039 #define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT … macro
H A Ddcn_3_1_4_sh_mask.h41075 #define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h36968 #define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h41780 #define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT … macro
H A Ddcn_3_2_0_sh_mask.h30219 #define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT … macro