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Searched refs:DP (Results 1 – 25 of 123) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_link_encoder.h54 SRI(DP_CONFIG, DP, id), \
55 SRI(DP_DPHY_CNTL, DP, id), \
56 SRI(DP_DPHY_PRBS_CNTL, DP, id), \
57 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
58 SRI(DP_DPHY_SYM0, DP, id), \
59 SRI(DP_DPHY_SYM1, DP, id), \
60 SRI(DP_DPHY_SYM2, DP, id), \
61 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
62 SRI(DP_LINK_CNTL, DP, id), \
63 SRI(DP_LINK_FRAMING_CNTL, DP, id), \
[all …]
H A Ddce_stream_encoder.h84 SRI(DP_MSE_RATE_CNTL, DP, id), \
85 SRI(DP_MSE_RATE_UPDATE, DP, id), \
86 SRI(DP_PIXEL_FORMAT, DP, id), \
87 SRI(DP_SEC_CNTL, DP, id), \
88 SRI(DP_STEER_FIFO, DP, id), \
89 SRI(DP_VID_M, DP, id), \
90 SRI(DP_VID_N, DP, id), \
91 SRI(DP_VID_STREAM_CNTL, DP, id), \
92 SRI(DP_VID_TIMING, DP, id), \
93 SRI(DP_SEC_AUD_N, DP, id), \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn30/
H A Ddcn30_dio_link_encoder.h36 SRI(DP_CONFIG, DP, id), \
37 SRI(DP_DPHY_CNTL, DP, id), \
38 SRI(DP_DPHY_PRBS_CNTL, DP, id), \
39 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
40 SRI(DP_DPHY_SYM0, DP, id), \
41 SRI(DP_DPHY_SYM1, DP, id), \
42 SRI(DP_DPHY_SYM2, DP, id), \
43 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
44 SRI(DP_LINK_CNTL, DP, id), \
45 SRI(DP_LINK_FRAMING_CNTL, DP, id), \
[all …]
H A Ddcn30_dio_stream_encoder.h76 SRI(DP_DB_CNTL, DP, id), \
77 SRI(DP_MSA_MISC, DP, id), \
78 SRI(DP_MSA_VBID_MISC, DP, id), \
79 SRI(DP_MSA_COLORIMETRY, DP, id), \
80 SRI(DP_MSA_TIMING_PARAM1, DP, id), \
81 SRI(DP_MSA_TIMING_PARAM2, DP, id), \
82 SRI(DP_MSA_TIMING_PARAM3, DP, id), \
83 SRI(DP_MSA_TIMING_PARAM4, DP, id), \
84 SRI(DP_MSE_RATE_CNTL, DP, id), \
85 SRI(DP_MSE_RATE_UPDATE, DP, id), \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn301/
H A Ddcn301_dio_link_encoder.h37 SRI(DP_CONFIG, DP, id), \
38 SRI(DP_DPHY_CNTL, DP, id), \
39 SRI(DP_DPHY_PRBS_CNTL, DP, id), \
40 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
41 SRI(DP_DPHY_SYM0, DP, id), \
42 SRI(DP_DPHY_SYM1, DP, id), \
43 SRI(DP_DPHY_SYM2, DP, id), \
44 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
45 SRI(DP_LINK_CNTL, DP, id), \
46 SRI(DP_LINK_FRAMING_CNTL, DP, id), \
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dg4x_dp.c122 intel_dp->DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED; in intel_dp_prepare()
125 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; in intel_dp_prepare()
126 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); in intel_dp_prepare()
132 intel_dp->DP |= DP_SYNC_HS_HIGH; in intel_dp_prepare()
134 intel_dp->DP |= DP_SYNC_VS_HIGH; in intel_dp_prepare()
135 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; in intel_dp_prepare()
138 intel_dp->DP |= DP_ENHANCED_FRAMING; in intel_dp_prepare()
140 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe); in intel_dp_prepare()
142 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; in intel_dp_prepare()
150 intel_dp->DP |= DP_COLOR_RANGE_16_235; in intel_dp_prepare()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.h107 SRI_ARR(DP_DB_CNTL, DP, id), \
108 SRI_ARR(DP_MSA_MISC, DP, id), \
109 SRI_ARR(DP_MSA_VBID_MISC, DP, id), \
110 SRI_ARR(DP_MSA_COLORIMETRY, DP, id), \
111 SRI_ARR(DP_MSA_TIMING_PARAM1, DP, id), \
112 SRI_ARR(DP_MSA_TIMING_PARAM2, DP, id), \
113 SRI_ARR(DP_MSA_TIMING_PARAM3, DP, id), \
114 SRI_ARR(DP_MSA_TIMING_PARAM4, DP, id), \
115 SRI_ARR(DP_MSE_RATE_CNTL, DP, id), \
116 SRI_ARR(DP_MSE_RATE_UPDATE, DP, id), \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn35/
H A Ddcn35_dio_stream_encoder.h75 SRI(DP_DB_CNTL, DP, id), \
76 SRI(DP_MSA_MISC, DP, id), \
77 SRI(DP_MSA_VBID_MISC, DP, id), \
78 SRI(DP_MSA_COLORIMETRY, DP, id), \
79 SRI(DP_MSA_TIMING_PARAM1, DP, id), \
80 SRI(DP_MSA_TIMING_PARAM2, DP, id), \
81 SRI(DP_MSA_TIMING_PARAM3, DP, id), \
82 SRI(DP_MSA_TIMING_PARAM4, DP, id), \
83 SRI(DP_MSE_RATE_CNTL, DP, id), \
84 SRI(DP_MSE_RATE_UPDATE, DP, id), \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn314/
H A Ddcn314_dio_stream_encoder.h77 SRI(DP_DB_CNTL, DP, id), \
78 SRI(DP_MSA_MISC, DP, id), \
79 SRI(DP_MSA_VBID_MISC, DP, id), \
80 SRI(DP_MSA_COLORIMETRY, DP, id), \
81 SRI(DP_MSA_TIMING_PARAM1, DP, id), \
82 SRI(DP_MSA_TIMING_PARAM2, DP, id), \
83 SRI(DP_MSA_TIMING_PARAM3, DP, id), \
84 SRI(DP_MSA_TIMING_PARAM4, DP, id), \
85 SRI(DP_MSE_RATE_CNTL, DP, id), \
86 SRI(DP_MSE_RATE_UPDATE, DP, id), \
[all …]
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_ethtool.c249 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" in bnx2x_get_vf_link_ksettings()
356 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" in bnx2x_get_link_ksettings()
385 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" in bnx2x_set_link_ksettings()
409 DP(BNX2X_MSG_ETHTOOL, in bnx2x_set_link_ksettings()
418 DP(BNX2X_MSG_ETHTOOL, in bnx2x_set_link_ksettings()
439 DP(BNX2X_MSG_ETHTOOL, in bnx2x_set_link_ksettings()
458 DP(BNX2X_MSG_ETHTOOL, in bnx2x_set_link_ksettings()
473 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); in bnx2x_set_link_ksettings()
483 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx); in bnx2x_set_link_ksettings()
492 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n"); in bnx2x_set_link_ksettings()
[all …]
H A Dbnx2x_dcb.c131 DP(NETIF_MSG_LINK, "local_mib.error %x\n", error); in bnx2x_dump_dcbx_drv_param()
134 DP(NETIF_MSG_LINK, in bnx2x_dump_dcbx_drv_param()
137 DP(NETIF_MSG_LINK, in bnx2x_dump_dcbx_drv_param()
141 DP(NETIF_MSG_LINK, in bnx2x_dump_dcbx_drv_param()
146 DP(BNX2X_MSG_DCB, "dcbx_features.pfc.pri_en_bitmap %x\n", in bnx2x_dump_dcbx_drv_param()
148 DP(BNX2X_MSG_DCB, "dcbx_features.pfc.pfc_caps %x\n", in bnx2x_dump_dcbx_drv_param()
150 DP(BNX2X_MSG_DCB, "dcbx_features.pfc.enabled %x\n", in bnx2x_dump_dcbx_drv_param()
153 DP(BNX2X_MSG_DCB, "dcbx_features.app.default_pri %x\n", in bnx2x_dump_dcbx_drv_param()
155 DP(BNX2X_MSG_DCB, "dcbx_features.app.tc_supported %x\n", in bnx2x_dump_dcbx_drv_param()
157 DP(BNX2X_MSG_DCB, "dcbx_features.app.enabled %x\n", in bnx2x_dump_dcbx_drv_param()
[all …]
H A Dbnx2x_link.c261 DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n"); in bnx2x_check_lfa()
302 DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n", in bnx2x_check_lfa()
311 DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n", in bnx2x_check_lfa()
320 DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n", in bnx2x_check_lfa()
331 DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n", in bnx2x_check_lfa()
344 DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n", in bnx2x_check_lfa()
357 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode, in bnx2x_check_lfa()
374 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin); in bnx2x_get_epio()
391 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin); in bnx2x_set_epio()
394 DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en); in bnx2x_set_epio()
[all …]
H A Dbnx2x_sriov.c100 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", in bnx2x_vf_igu_ack_sb()
105 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", in bnx2x_vf_igu_ack_sb()
119 DP(BNX2X_MSG_IOV, "Slowpath objects not yet initialized!\n"); in bnx2x_validate_vf_sp_objs()
131 DP(BNX2X_MSG_IOV, in bnx2x_vfop_qctor_dump_tx()
149 …DP(BNX2X_MSG_IOV, "VF[%d] Q_SETUP: rxq[%d]-- vfsb=%d, sb-index=%d, hc-rate=%d, mtu=%d, buf-size=%d… in bnx2x_vfop_qctor_dump_rx()
241 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); in bnx2x_vf_queue_create()
250 DP(BNX2X_MSG_IOV, "queue was already up. Aborting gracefully\n"); in bnx2x_vf_queue_create()
283 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); in bnx2x_vf_queue_destroy()
292 DP(BNX2X_MSG_IOV, "queue was already stopped. Aborting gracefully\n"); in bnx2x_vf_queue_destroy()
340 DP(BNX2X_MSG_IOV, "vf[%d] - deleting all %s\n", vf->abs_vfid, in bnx2x_vf_vlan_mac_clear()
[all …]
H A Dbnx2x_main.c412 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
420 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
430 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
438 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
448 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
455 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
465 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n", in bnx2x_dp_dmae()
880 DP(NETIF_MSG_IFDOWN, in bnx2x_hc_int_disable()
897 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val); in bnx2x_igu_int_disable()
927 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); in bnx2x_panic_dump()
[all …]
H A Dbnx2x_sp.c77 DP(BNX2X_MSG_SP, "Setup the execution queue with the chunk length of %d\n", in bnx2x_exe_queue_init()
84 DP(BNX2X_MSG_SP, "Deleting an exe_queue element\n"); in bnx2x_exe_queue_free_elem()
131 DP(BNX2X_MSG_SP, "Preamble failed: %d\n", rc); in bnx2x_exe_queue_add()
192 DP(BNX2X_MSG_SP, "RAMROD_DRV_CLR_ONLY requested: resetting a pending_comp list\n"); in bnx2x_exe_queue_step()
253 DP(BNX2X_MSG_SP, "Allocating a new exe_queue element\n"); in bnx2x_exe_queue_alloc_elem()
294 DP(BNX2X_MSG_SP, "waiting for state to become %d\n", state); in bnx2x_state_wait()
300 DP(BNX2X_MSG_SP, "exit (cnt %d)\n", 5000 - cnt); in bnx2x_state_wait()
436 DP(BNX2X_MSG_SP, "vlan_mac_lock writer - There are readers; Busy\n"); in __bnx2x_vlan_mac_h_write_trylock()
440 DP(BNX2X_MSG_SP, "vlan_mac_lock writer - Taken\n"); in __bnx2x_vlan_mac_h_write_trylock()
459 DP(BNX2X_MSG_SP, "vlan_mac_lock execute pending command with ramrod flags %lu\n", in __bnx2x_vlan_mac_h_exec_pending()
[all …]
H A Dbnx2x_vfpf.c45 DP(BNX2X_MSG_IOV, "preparing to send %d tlv over vf pf channel\n", in bnx2x_vfpf_prep()
62 DP(BNX2X_MSG_IOV, "done sending [%d] tlv over vf pf channel\n", in bnx2x_vfpf_finalize()
87 DP(BNX2X_MSG_IOV, "TLV list does not contain %d TLV\n", req_tlv); in bnx2x_search_tlv_list()
100 DP(BNX2X_MSG_IOV, "TLV number %d: type %d, length %d\n", i, in bnx2x_dp_tlv_list()
119 DP(BNX2X_MSG_IOV, "TLV number %d: type %d, length %d\n", i, in bnx2x_dp_tlv_list()
158 DP(BNX2X_MSG_IOV, "detecting channel down. Aborting message\n"); in bnx2x_send_msg2pf()
190 DP(BNX2X_MSG_SP, "Got a response from PF\n"); in bnx2x_send_msg2pf()
216 DP(BNX2X_MSG_IOV, "valid ME register value: 0x%08x\n", me_reg); in bnx2x_get_vf_id()
274 DP(BNX2X_MSG_SP, "attempting to acquire resources\n"); in bnx2x_vfpf_acquire()
294 DP(BNX2X_MSG_SP, "resources acquired\n"); in bnx2x_vfpf_acquire()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn10/
H A Ddcn10_link_encoder.h47 SRI(DP_CONFIG, DP, id), \
48 SRI(DP_DPHY_CNTL, DP, id), \
49 SRI(DP_DPHY_PRBS_CNTL, DP, id), \
50 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
51 SRI(DP_DPHY_SYM0, DP, id), \
52 SRI(DP_DPHY_SYM1, DP, id), \
53 SRI(DP_DPHY_SYM2, DP, id), \
54 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
55 SRI(DP_LINK_CNTL, DP, id), \
56 SRI(DP_LINK_FRAMING_CNTL, DP, id), \
[all …]
H A Ddcn10_stream_encoder.h74 SRI(DP_DB_CNTL, DP, id), \
75 SRI(DP_MSA_MISC, DP, id), \
76 SRI(DP_MSA_VBID_MISC, DP, id), \
77 SRI(DP_MSA_COLORIMETRY, DP, id), \
78 SRI(DP_MSA_TIMING_PARAM1, DP, id), \
79 SRI(DP_MSA_TIMING_PARAM2, DP, id), \
80 SRI(DP_MSA_TIMING_PARAM3, DP, id), \
81 SRI(DP_MSA_TIMING_PARAM4, DP, id), \
82 SRI(DP_MSE_RATE_CNTL, DP, id), \
83 SRI(DP_MSE_RATE_UPDATE, DP, id), \
[all …]
/linux/Documentation/sound/hd-audio/
H A Ddp-mst.rst2 HD-Audio DP-MST Support
5 To support DP MST audio, HD Audio hdmi codec driver introduces virtual pin
8 Virtual pin is an extension of per_pin. The most difference of DP MST
9 from legacy is that DP MST introduces device entry. Each pin can contain
25 the device entries number is dynamically changed. If DP MST hub is connected,
26 it is in DP MST mode, and the device entries number is 3. Otherwise, the
30 when bootup no matter whether it is in DP MST mode or not.
34 DP MST reuses connection list code. The code can be reused because
37 This means DP MST gets the device entry connection list without the
/linux/Documentation/devicetree/bindings/display/bridge/
H A Dmegachips-stdpxxxx-ge-b850v3-fw.txt2 STDP4028-ge-b850v3-fw bridges (LVDS-DP)
3 STDP2690-ge-b850v3-fw bridges (DP-DP++)
7 Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output
/linux/drivers/gpu/drm/bridge/cadence/
H A DKconfig25 tristate "Cadence DPI/DP bridge"
33 Support Cadence DPI to DP bridge. This is an internal
36 in DP format.
42 bool "J721E Cadence DPI/DP wrapper support"
45 Support J721E Cadence DPI/DP wrapper. This is a wrapper
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.h283 SRI_ARR(DP_DB_CNTL, DP, id), SRI_ARR(DP_MSA_MISC, DP, id), \
284 SRI_ARR(DP_MSA_VBID_MISC, DP, id), SRI_ARR(DP_MSA_COLORIMETRY, DP, id), \
285 SRI_ARR(DP_MSA_TIMING_PARAM1, DP, id), \
286 SRI_ARR(DP_MSA_TIMING_PARAM2, DP, id), \
287 SRI_ARR(DP_MSA_TIMING_PARAM3, DP, id), \
288 SRI_ARR(DP_MSA_TIMING_PARAM4, DP, id), \
289 SRI_ARR(DP_MSE_RATE_CNTL, DP, id), SRI_ARR(DP_MSE_RATE_UPDATE, DP, id), \
290 SRI_ARR(DP_PIXEL_FORMAT, DP, id), SRI_ARR(DP_SEC_CNTL, DP, id), \
291 SRI_ARR(DP_SEC_CNTL1, DP, id), SRI_ARR(DP_SEC_CNTL2, DP, id), \
292 SRI_ARR(DP_SEC_CNTL5, DP, id), SRI_ARR(DP_SEC_CNTL6, DP, id), \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.h198 SRI_ARR(DP_DB_CNTL, DP, id), SRI_ARR(DP_MSA_MISC, DP, id), \
199 SRI_ARR(DP_MSA_VBID_MISC, DP, id), SRI_ARR(DP_MSA_COLORIMETRY, DP, id), \
200 SRI_ARR(DP_MSA_TIMING_PARAM1, DP, id), \
201 SRI_ARR(DP_MSA_TIMING_PARAM2, DP, id), \
202 SRI_ARR(DP_MSA_TIMING_PARAM3, DP, id), \
203 SRI_ARR(DP_MSA_TIMING_PARAM4, DP, id), \
204 SRI_ARR(DP_MSE_RATE_CNTL, DP, id), SRI_ARR(DP_MSE_RATE_UPDATE, DP, id), \
205 SRI_ARR(DP_PIXEL_FORMAT, DP, id), SRI_ARR(DP_SEC_CNTL, DP, id), \
206 SRI_ARR(DP_SEC_CNTL1, DP, id), SRI_ARR(DP_SEC_CNTL2, DP, id), \
207 SRI_ARR(DP_SEC_CNTL5, DP, id), SRI_ARR(DP_SEC_CNTL6, DP, id), \
[all …]
/linux/drivers/gpu/drm/display/
H A DKconfig34 bool "DRM DP AUX Interface"
38 read and write values to arbitrary DPCD registers on the DP aux
51 DP tunnel features like the Bandwidth Allocation mode to maximize the
55 bool "Enable debugging the DP tunnel state"
61 Enables debugging the DP tunnel manager's state, including the
/linux/drivers/gpu/drm/gma500/
H A Dcdv_intel_dp.c256 uint32_t DP; member
1044 intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; in cdv_intel_dp_mode_set()
1045 intel_dp->DP |= intel_dp->color_range; in cdv_intel_dp_mode_set()
1048 intel_dp->DP |= DP_SYNC_HS_HIGH; in cdv_intel_dp_mode_set()
1050 intel_dp->DP |= DP_SYNC_VS_HIGH; in cdv_intel_dp_mode_set()
1052 intel_dp->DP |= DP_LINK_TRAIN_OFF; in cdv_intel_dp_mode_set()
1056 intel_dp->DP |= DP_PORT_WIDTH_1; in cdv_intel_dp_mode_set()
1059 intel_dp->DP |= DP_PORT_WIDTH_2; in cdv_intel_dp_mode_set()
1062 intel_dp->DP |= DP_PORT_WIDTH_4; in cdv_intel_dp_mode_set()
1066 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; in cdv_intel_dp_mode_set()
[all …]

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