Home
last modified time | relevance | path

Searched refs:DP (Results 1 – 25 of 80) sorted by relevance

1234

/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_link_encoder.h54 SRI(DP_CONFIG, DP, id), \
55 SRI(DP_DPHY_CNTL, DP, id), \
56 SRI(DP_DPHY_PRBS_CNTL, DP, id), \
57 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
58 SRI(DP_DPHY_SYM0, DP, id), \
59 SRI(DP_DPHY_SYM1, DP, id), \
60 SRI(DP_DPHY_SYM2, DP, id), \
61 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
62 SRI(DP_LINK_CNTL, DP, id), \
63 SRI(DP_LINK_FRAMING_CNTL, DP, id), \
[all …]
H A Ddce_stream_encoder.h85 SRI(DP_MSE_RATE_CNTL, DP, id), \
86 SRI(DP_MSE_RATE_UPDATE, DP, id), \
87 SRI(DP_PIXEL_FORMAT, DP, id), \
88 SRI(DP_SEC_CNTL, DP, id), \
89 SRI(DP_STEER_FIFO, DP, id), \
90 SRI(DP_VID_M, DP, id), \
91 SRI(DP_VID_N, DP, id), \
92 SRI(DP_VID_STREAM_CNTL, DP, id), \
93 SRI(DP_VID_TIMING, DP, id), \
94 SRI(DP_SEC_AUD_N, DP, id), \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn30/
H A Ddcn30_dio_link_encoder.h36 SRI(DP_CONFIG, DP, id), \
37 SRI(DP_DPHY_CNTL, DP, id), \
38 SRI(DP_DPHY_PRBS_CNTL, DP, id), \
39 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
40 SRI(DP_DPHY_SYM0, DP, id), \
41 SRI(DP_DPHY_SYM1, DP, id), \
42 SRI(DP_DPHY_SYM2, DP, id), \
43 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
44 SRI(DP_LINK_CNTL, DP, id), \
45 SRI(DP_LINK_FRAMING_CNTL, DP, id), \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn301/
H A Ddcn301_dio_link_encoder.h37 SRI(DP_CONFIG, DP, id), \
38 SRI(DP_DPHY_CNTL, DP, id), \
39 SRI(DP_DPHY_PRBS_CNTL, DP, id), \
40 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
41 SRI(DP_DPHY_SYM0, DP, id), \
42 SRI(DP_DPHY_SYM1, DP, id), \
43 SRI(DP_DPHY_SYM2, DP, id), \
44 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
45 SRI(DP_LINK_CNTL, DP, id), \
46 SRI(DP_LINK_FRAMING_CNTL, DP, id), \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn35/
H A Ddcn35_dio_stream_encoder.h75 SRI(DP_DB_CNTL, DP, id), \
76 SRI(DP_MSA_MISC, DP, id), \
77 SRI(DP_MSA_VBID_MISC, DP, id), \
78 SRI(DP_MSA_COLORIMETRY, DP, id), \
79 SRI(DP_MSA_TIMING_PARAM1, DP, id), \
80 SRI(DP_MSA_TIMING_PARAM2, DP, id), \
81 SRI(DP_MSA_TIMING_PARAM3, DP, id), \
82 SRI(DP_MSA_TIMING_PARAM4, DP, id), \
83 SRI(DP_MSE_RATE_CNTL, DP, id), \
84 SRI(DP_MSE_RATE_UPDATE, DP, id), \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn314/
H A Ddcn314_dio_stream_encoder.h77 SRI(DP_DB_CNTL, DP, id), \
78 SRI(DP_MSA_MISC, DP, id), \
79 SRI(DP_MSA_VBID_MISC, DP, id), \
80 SRI(DP_MSA_COLORIMETRY, DP, id), \
81 SRI(DP_MSA_TIMING_PARAM1, DP, id), \
82 SRI(DP_MSA_TIMING_PARAM2, DP, id), \
83 SRI(DP_MSA_TIMING_PARAM3, DP, id), \
84 SRI(DP_MSA_TIMING_PARAM4, DP, id), \
85 SRI(DP_MSE_RATE_CNTL, DP, id), \
86 SRI(DP_MSE_RATE_UPDATE, DP, id), \
[all …]
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_dcb.c131 DP(NETIF_MSG_LINK, "local_mib.error %x\n", error); in bnx2x_dump_dcbx_drv_param()
134 DP(NETIF_MSG_LINK, in bnx2x_dump_dcbx_drv_param()
137 DP(NETIF_MSG_LINK, in bnx2x_dump_dcbx_drv_param()
141 DP(NETIF_MSG_LINK, in bnx2x_dump_dcbx_drv_param()
146 DP(BNX2X_MSG_DCB, "dcbx_features.pfc.pri_en_bitmap %x\n", in bnx2x_dump_dcbx_drv_param()
148 DP(BNX2X_MSG_DCB, "dcbx_features.pfc.pfc_caps %x\n", in bnx2x_dump_dcbx_drv_param()
150 DP(BNX2X_MSG_DCB, "dcbx_features.pfc.enabled %x\n", in bnx2x_dump_dcbx_drv_param()
153 DP(BNX2X_MSG_DCB, "dcbx_features.app.default_pri %x\n", in bnx2x_dump_dcbx_drv_param()
155 DP(BNX2X_MSG_DCB, "dcbx_features.app.tc_supported %x\n", in bnx2x_dump_dcbx_drv_param()
157 DP(BNX2X_MSG_DCB, "dcbx_features.app.enabled %x\n", in bnx2x_dump_dcbx_drv_param()
[all …]
H A Dbnx2x_link.c261 DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n"); in bnx2x_check_lfa()
302 DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n", in bnx2x_check_lfa()
311 DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n", in bnx2x_check_lfa()
320 DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n", in bnx2x_check_lfa()
331 DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n", in bnx2x_check_lfa()
344 DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n", in bnx2x_check_lfa()
357 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode, in bnx2x_check_lfa()
374 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin); in bnx2x_get_epio()
391 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin); in bnx2x_set_epio()
394 DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en); in bnx2x_set_epio()
[all …]
H A Dbnx2x_sriov.c100 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", in bnx2x_vf_igu_ack_sb()
105 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", in bnx2x_vf_igu_ack_sb()
119 DP(BNX2X_MSG_IOV, "Slowpath objects not yet initialized!\n"); in bnx2x_validate_vf_sp_objs()
131 DP(BNX2X_MSG_IOV, in bnx2x_vfop_qctor_dump_tx()
149 …DP(BNX2X_MSG_IOV, "VF[%d] Q_SETUP: rxq[%d]-- vfsb=%d, sb-index=%d, hc-rate=%d, mtu=%d, buf-size=%d… in bnx2x_vfop_qctor_dump_rx()
241 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); in bnx2x_vf_queue_create()
250 DP(BNX2X_MSG_IOV, "queue was already up. Aborting gracefully\n"); in bnx2x_vf_queue_create()
283 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); in bnx2x_vf_queue_destroy()
292 DP(BNX2X_MSG_IOV, "queue was already stopped. Aborting gracefully\n"); in bnx2x_vf_queue_destroy()
340 DP(BNX2X_MSG_IOV, "vf[%d] - deleting all %s\n", vf->abs_vfid, in bnx2x_vf_vlan_mac_clear()
[all …]
H A Dbnx2x_main.c415 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
423 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
433 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
441 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
451 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
458 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
468 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n", in bnx2x_dp_dmae()
883 DP(NETIF_MSG_IFDOWN, in bnx2x_hc_int_disable()
900 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val); in bnx2x_igu_int_disable()
930 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); in bnx2x_panic_dump()
[all …]
H A Dbnx2x_sp.c77 DP(BNX2X_MSG_SP, "Setup the execution queue with the chunk length of %d\n", in bnx2x_exe_queue_init()
84 DP(BNX2X_MSG_SP, "Deleting an exe_queue element\n"); in bnx2x_exe_queue_free_elem()
131 DP(BNX2X_MSG_SP, "Preamble failed: %d\n", rc); in bnx2x_exe_queue_add()
192 DP(BNX2X_MSG_SP, "RAMROD_DRV_CLR_ONLY requested: resetting a pending_comp list\n"); in bnx2x_exe_queue_step()
253 DP(BNX2X_MSG_SP, "Allocating a new exe_queue element\n"); in bnx2x_exe_queue_alloc_elem()
294 DP(BNX2X_MSG_SP, "waiting for state to become %d\n", state); in bnx2x_state_wait()
300 DP(BNX2X_MSG_SP, "exit (cnt %d)\n", 5000 - cnt); in bnx2x_state_wait()
436 DP(BNX2X_MSG_SP, "vlan_mac_lock writer - There are readers; Busy\n"); in __bnx2x_vlan_mac_h_write_trylock()
440 DP(BNX2X_MSG_SP, "vlan_mac_lock writer - Taken\n"); in __bnx2x_vlan_mac_h_write_trylock()
459 DP(BNX2X_MSG_SP, "vlan_mac_lock execute pending command with ramrod flags %lu\n", in __bnx2x_vlan_mac_h_exec_pending()
[all …]
H A Dbnx2x_vfpf.c45 DP(BNX2X_MSG_IOV, "preparing to send %d tlv over vf pf channel\n", in bnx2x_vfpf_prep()
62 DP(BNX2X_MSG_IOV, "done sending [%d] tlv over vf pf channel\n", in bnx2x_vfpf_finalize()
87 DP(BNX2X_MSG_IOV, "TLV list does not contain %d TLV\n", req_tlv); in bnx2x_search_tlv_list()
100 DP(BNX2X_MSG_IOV, "TLV number %d: type %d, length %d\n", i, in bnx2x_dp_tlv_list()
119 DP(BNX2X_MSG_IOV, "TLV number %d: type %d, length %d\n", i, in bnx2x_dp_tlv_list()
158 DP(BNX2X_MSG_IOV, "detecting channel down. Aborting message\n"); in bnx2x_send_msg2pf()
190 DP(BNX2X_MSG_SP, "Got a response from PF\n"); in bnx2x_send_msg2pf()
216 DP(BNX2X_MSG_IOV, "valid ME register value: 0x%08x\n", me_reg); in bnx2x_get_vf_id()
274 DP(BNX2X_MSG_SP, "attempting to acquire resources\n"); in bnx2x_vfpf_acquire()
294 DP(BNX2X_MSG_SP, "resources acquired\n"); in bnx2x_vfpf_acquire()
[all …]
H A Dbnx2x_cmn.c209 DP(NETIF_MSG_TX_DONE, "fp[%d]: pkt_idx %d buff @(%p)->skb %p\n", in bnx2x_free_tx_pkt()
296 DP(NETIF_MSG_TX_DONE, in bnx2x_tx_int()
371 DP(NETIF_MSG_RX_STATUS, "fp_cqe->sgl[%d] = %d\n", in bnx2x_update_sge_prod()
402 DP(NETIF_MSG_RX_STATUS, in bnx2x_update_sge_prod()
489 DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%llx\n", in bnx2x_tpa_start()
821 DP(NETIF_MSG_RX_STATUS, in bnx2x_tpa_stop()
835 DP(NETIF_MSG_RX_STATUS, in bnx2x_tpa_stop()
920 DP(NETIF_MSG_RX_STATUS, in bnx2x_rx_int()
956 DP(NETIF_MSG_RX_STATUS, in bnx2x_rx_int()
987 DP(NETIF_MSG_RX_STATUS, in bnx2x_rx_int()
[all …]
H A Dbnx2x_cmn.h57 DP(NETIF_MSG_HW, \
67 DP(NETIF_MSG_HW, \
531 DP(NETIF_MSG_RX_STATUS, in bnx2x_update_rx_prod()
648 DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n", in bnx2x_igu_ack_sb_gen()
711 DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n", in bnx2x_igu_ack_int()
940 DP(NETIF_MSG_IFUP, "Configuring ethertype 0x88a8 for BD\n"); in bnx2x_func_start()
950 DP(NETIF_MSG_IFUP, in bnx2x_func_start()
1172 DP(NETIF_MSG_IFUP, "created tx data cid %d, txq %d\n", in bnx2x_init_txdata()
1290 DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL, in bnx2x_extract_max_cfg()
1361 DP(NETIF_MSG_IFUP, "drv_flags 0x%08x\n", drv_flags); in bnx2x_update_drv_flags()
H A Dbnx2x_stats.c88 DP(BNX2X_MSG_STATS, "dumping stats:\n" in bnx2x_dp_stats()
104 DP(BNX2X_MSG_STATS, in bnx2x_dp_stats()
136 DP(BNX2X_MSG_STATS, "Sending statistics ramrod %d\n", in bnx2x_storm_stats_post()
828 DP(BNX2X_MSG_STATS, in bnx2x_hw_stats_update()
888 DP(BNX2X_MSG_STATS, in bnx2x_storm_stats_validate_counters()
895 DP(BNX2X_MSG_STATS, in bnx2x_storm_stats_validate_counters()
902 DP(BNX2X_MSG_STATS, in bnx2x_storm_stats_validate_counters()
909 DP(BNX2X_MSG_STATS, in bnx2x_storm_stats_validate_counters()
959 DP(BNX2X_MSG_STATS, "queue[%d]: ucast_sent 0x%x, bcast_sent 0x%x mcast_sent 0x%x\n", in bnx2x_storm_stats_update()
963 DP(BNX2X_MSG_STATS, "---------------\n"); in bnx2x_storm_stats_update()
[all …]
/linux/Documentation/sound/hd-audio/
H A Ddp-mst.rst2 HD-Audio DP-MST Support
5 To support DP MST audio, HD Audio hdmi codec driver introduces virtual pin
8 Virtual pin is an extension of per_pin. The most difference of DP MST
9 from legacy is that DP MST introduces device entry. Each pin can contain
25 the device entries number is dynamically changed. If DP MST hub is connected,
26 it is in DP MST mode, and the device entries number is 3. Otherwise, the
30 when bootup no matter whether it is in DP MST mode or not.
34 DP MST reuses connection list code. The code can be reused because
37 This means DP MST gets the device entry connection list without the
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn10/
H A Ddcn10_stream_encoder.h74 SRI(DP_DB_CNTL, DP, id), \
75 SRI(DP_MSA_MISC, DP, id), \
76 SRI(DP_MSA_VBID_MISC, DP, id), \
77 SRI(DP_MSA_COLORIMETRY, DP, id), \
78 SRI(DP_MSA_TIMING_PARAM1, DP, id), \
79 SRI(DP_MSA_TIMING_PARAM2, DP, id), \
80 SRI(DP_MSA_TIMING_PARAM3, DP, id), \
81 SRI(DP_MSA_TIMING_PARAM4, DP, id), \
82 SRI(DP_MSE_RATE_CNTL, DP, id), \
83 SRI(DP_MSE_RATE_UPDATE, DP, id), \
[all …]
/linux/drivers/gpu/drm/gma500/
H A Dcdv_intel_dp.c257 uint32_t DP; member
1044 intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; in cdv_intel_dp_mode_set()
1045 intel_dp->DP |= intel_dp->color_range; in cdv_intel_dp_mode_set()
1048 intel_dp->DP |= DP_SYNC_HS_HIGH; in cdv_intel_dp_mode_set()
1050 intel_dp->DP |= DP_SYNC_VS_HIGH; in cdv_intel_dp_mode_set()
1052 intel_dp->DP |= DP_LINK_TRAIN_OFF; in cdv_intel_dp_mode_set()
1056 intel_dp->DP |= DP_PORT_WIDTH_1; in cdv_intel_dp_mode_set()
1059 intel_dp->DP |= DP_PORT_WIDTH_2; in cdv_intel_dp_mode_set()
1062 intel_dp->DP |= DP_PORT_WIDTH_4; in cdv_intel_dp_mode_set()
1066 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; in cdv_intel_dp_mode_set()
[all …]
/linux/Documentation/gpu/
H A Dzynqmp.rst18 though debugfs. The following files in /sys/kernel/debug/dri/X/DP-1/test/
95 for prop in /sys/kernel/debug/dri/1/DP-1/test/*; do
125 echo 1 > /sys/kernel/debug/dri/1/DP-1/test/enhanced
126 echo tps1 > /sys/kernel/debug/dri/1/DP-1/test/pattern
127 echo 1620000000 > /sys/kernel/debug/dri/1/DP-1/test/rate
128 echo 1 > /sys/kernel/debug/dri/1/DP-1/test/ignore_aux_errors
129 echo 1 > /sys/kernel/debug/dri/1/DP-1/test/ignore_hpd
130 echo 1 > /sys/kernel/debug/dri/1/DP-1/test/active
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn20/
H A Ddcn20_stream_encoder.h37 SRI(DP_DSC_CNTL, DP, id), \
38 SRI(DP_DSC_BYTES_PER_PIXEL, DP, id), \
40 SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \
42 SRI(DP_SEC_FRAMING4, DP, id)
/linux/net/sched/
H A Dsch_gred.c35 u32 DP; /* the drop parameters */ member
503 q->DP = dp; in gred_change_vq()
676 if (ctl->DP >= table->DPs) { in gred_change()
682 err = gred_vqs_validate(table, ctl->DP, tb[TCA_GRED_VQ_LIST], in gred_change()
696 "setting default to %d\n", ctl->DP, def_prio); in gred_change()
706 err = gred_change_vq(sch, ctl->DP, ctl, prio, stab, max_P, &prealloc, in gred_change()
818 opt.DP = MAX_DPs + i; in gred_dump()
823 opt.DP = q->DP; in gred_dump()
867 if (nla_put_u32(skb, TCA_GRED_VQ_DP, q->DP)) in gred_dump()
/linux/sound/hda/codecs/hdmi/
H A DKconfig8 This will enable all HDMI/DP codec drivers as default, but you can
24 to assure the multiple streams for DP-MST support.
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65-iot2050-common-pg2.dtsi33 /* Workaround needed to get DP clock of 154Mhz */
/linux/Documentation/driver-api/media/drivers/
H A Dtuners.rst25 TCP [ABCJLMNQ] 90[89][125] [DP] [ACD] 27 [ABCD]
39 [DP]:
/linux/drivers/gpu/drm/xe/
H A DKconfig66 bool "Enable DP tunnel support"
72 Choose this option to detect DP tunnels and enable the Bandwidth

1234