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Searched refs:DML2_MAX_PLANES (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/
H A Ddml2_core_shared_types.h265 enum dml2_pstate_change_support DRAMClockChangeSupport[DML2_MAX_PLANES];
266 enum dml2_pstate_change_support FCLKChangeSupport[DML2_MAX_PLANES];
267 enum dml2_pstate_change_support temp_read_or_ppt_support[DML2_MAX_PLANES];
290 …bool MPCCombineEnable[DML2_MAX_PLANES]; /// <brief Indicate if the MPC Combine enable in the given…
291 …enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; /// <brief ODM mode that is chosen in the mode check …
292 …unsigned int DPPPerSurface[DML2_MAX_PLANES]; /// <brief How many DPPs are needed drive the surface…
293 …bool DSCEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the DSC is actually required; used in mod…
294 bool FECEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the FEC is actually required
295 …unsigned int NumberOfDSCSlices[DML2_MAX_PLANES]; /// <brief Indicate how many slices needed to sup…
297 double OutputBpp[DML2_MAX_PLANES];
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H A Ddml2_core_utils.c405 for (unsigned int k = 0; k < DML2_MAX_PLANES; ++k) { in dml2_core_utils_pipe_plane_mapping()
409 for (unsigned int plane_idx = 0; plane_idx < DML2_MAX_PLANES; plane_idx++) { in dml2_core_utils_pipe_plane_mapping()
619 memset(scratch->main_stream_index_from_svp_stream_index, 0, sizeof(int) * DML2_MAX_PLANES); in dml2_core_utils_expand_implict_subvp()
620 memset(scratch->svp_stream_index_from_main_stream_index, 0, sizeof(int) * DML2_MAX_PLANES); in dml2_core_utils_expand_implict_subvp()
621 memset(scratch->main_plane_index_to_phantom_plane_index, 0, sizeof(int) * DML2_MAX_PLANES); in dml2_core_utils_expand_implict_subvp()
H A Ddml2_core_dcn4.c312 memset(scratch->main_stream_index_from_svp_stream_index, 0, sizeof(int) * DML2_MAX_PLANES); in expand_implict_subvp()
313 memset(scratch->svp_stream_index_from_main_stream_index, 0, sizeof(int) * DML2_MAX_PLANES); in expand_implict_subvp()
314 memset(scratch->main_plane_index_to_phantom_plane_index, 0, sizeof(int) * DML2_MAX_PLANES); in expand_implict_subvp()
H A Ddml2_core_dcn4_calcs.c221 for (unsigned int k = 0; k < DML2_MAX_PLANES; ++k) { in dml_calc_pipe_plane_mapping()
225 for (unsigned int plane_idx = 0; plane_idx < DML2_MAX_PLANES; plane_idx++) { in dml_calc_pipe_plane_mapping()
1030 bool DETPieceAssignedToThisSurfaceAlready[DML2_MAX_PLANES]; in CalculateDETBufferSize()
3528 double DCFClkDeepSleepPerSurface[DML2_MAX_PLANES]; in CalculateDCFCLKDeepSleepTdlut()
3617 double zero_double[DML2_MAX_PLANES]; in CalculateDCFCLKDeepSleep()
3618 unsigned int zero_integer[DML2_MAX_PLANES]; in CalculateDCFCLKDeepSleep()
3620 memset(zero_double, 0, DML2_MAX_PLANES * sizeof(double)); in CalculateDCFCLKDeepSleep()
3621 memset(zero_integer, 0, DML2_MAX_PLANES * sizeof(unsigned int)); in CalculateDCFCLKDeepSleep()
3708 unsigned int MaximumSwathHeightY[DML2_MAX_PLANES] = { 0 }; in CalculateSwathAndDETConfiguration()
3709 unsigned int MaximumSwathHeightC[DML2_MAX_PLANES] = { 0 }; in CalculateSwathAndDETConfiguration()
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/
H A Ddml_top_display_cfg_types.h10 #define DML2_MAX_PLANES 8 macro
457 struct dml2_plane_parameters plane_descriptors[DML2_MAX_PLANES];
458 struct dml2_stream_parameters stream_descriptors[DML2_MAX_PLANES];
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/
H A Ddml21_utils.c506 …>bw_ctx.bw.dcn.fams2_stream_base_params, 0, sizeof(union dmub_cmd_fams2_config) * DML2_MAX_PLANES); in dml21_build_fams2_programming()
507 …->bw_ctx.bw.dcn.fams2_stream_sub_params, 0, sizeof(union dmub_cmd_fams2_config) * DML2_MAX_PLANES); in dml21_build_fams2_programming()
508 …s2_stream_sub_params_v2, 0, sizeof(union dmub_fams2_stream_static_sub_state_v2) * DML2_MAX_PLANES); in dml21_build_fams2_programming()
H A Ddml21_wrapper_fpu.c79 for (dml_prog_idx = 0; dml_prog_idx < DML2_MAX_PLANES; dml_prog_idx++) { in dml21_calculate_rq_and_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/
H A Ddml2_pmo_dcn4_fams2.c556 enum dml2_pstate_method per_stream_variant_method[DML2_MAX_PLANES]; in expand_variant_strategy()
1072 for (i = 0; i < DML2_MAX_PLANES; i++) { in all_timings_support_drr()
1117 unsigned int num_planes_per_stream[DML2_MAX_PLANES] = { 0 }; in all_timings_support_svp()
1153 for (i = 0; i < DML2_MAX_PLANES; i++) { in all_timings_support_svp()
1253 for (i = 0; i < DML2_MAX_PLANES; i++) { in all_planes_match_method()
1388 memset(s->pmo_dcn4.sorted_group_gtl_disallow_index, 0, sizeof(unsigned int) * DML2_MAX_PLANES); in is_config_schedulable()
1670 for (i = 0; i < DML2_MAX_PLANES; i++) { in dcn4_get_vactive_pstate_margin()
1685 for (i = 0; i < DML2_MAX_PLANES; i++) { in get_vactive_det_fill_latency_delay_us()
2179 sizeof(struct dml2_pstate_meta) * DML2_MAX_PLANES); in setup_display_config()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/
H A Ddml2_dpmm_dcn4.c459 unsigned int remap_array[DML2_MAX_PLANES]; in are_timings_trivially_synchronizable()
497 unsigned int remap_array[DML2_MAX_PLANES]; in find_smallest_idle_time_in_vblank_us()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/
H A Ddml2_top_soc15.c86 …rt, l->test_mcache.validate_admissibility_params.per_plane_status, sizeof(bool) * DML2_MAX_PLANES); in dml2_top_optimization_test_function_mcache()
1027 …memset(params->per_plane_pipe_mcache_regs, 0, DML2_MAX_PLANES * DML2_MAX_DCN_PIPES * sizeof(struct… in dml2_top_soc15_build_mcache_programming()