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Searched refs:DML2_MAX_PLANES (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/
H A Ddml2_core_shared_types.h275 enum dml2_pstate_change_support DRAMClockChangeSupport[DML2_MAX_PLANES];
276 enum dml2_pstate_change_support FCLKChangeSupport[DML2_MAX_PLANES];
277 enum dml2_pstate_change_support temp_read_or_ppt_support[DML2_MAX_PLANES];
300 …bool MPCCombineEnable[DML2_MAX_PLANES]; /// <brief Indicate if the MPC Combine enable in the given…
301 …enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; /// <brief ODM mode that is chosen in the mode check …
302 …unsigned int DPPPerSurface[DML2_MAX_PLANES]; /// <brief How many DPPs are needed drive the surface…
303 …bool DSCEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the DSC is actually required; used in mod…
304 bool FECEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the FEC is actually required
305 …unsigned int NumberOfDSCSlices[DML2_MAX_PLANES]; /// <brief Indicate how many slices needed to sup…
307 double OutputBpp[DML2_MAX_PLANES];
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H A Ddml2_core_utils.c405 for (unsigned int k = 0; k < DML2_MAX_PLANES; ++k) { in dml2_core_utils_pipe_plane_mapping()
409 for (unsigned int plane_idx = 0; plane_idx < DML2_MAX_PLANES; plane_idx++) { in dml2_core_utils_pipe_plane_mapping()
619 memset(scratch->main_stream_index_from_svp_stream_index, 0, sizeof(int) * DML2_MAX_PLANES); in dml2_core_utils_expand_implict_subvp()
620 memset(scratch->svp_stream_index_from_main_stream_index, 0, sizeof(int) * DML2_MAX_PLANES); in dml2_core_utils_expand_implict_subvp()
621 memset(scratch->main_plane_index_to_phantom_plane_index, 0, sizeof(int) * DML2_MAX_PLANES); in dml2_core_utils_expand_implict_subvp()
H A Ddml2_core_dcn6_calcs_dchub.c693 DML_ASSERT(l->plane_idx < DML2_MAX_PLANES); in dcn6_rq_dlg_get_dlg_reg()
707 if (l->plane_idx < DML2_MAX_PLANES) { in dcn6_rq_dlg_get_dlg_reg()
744 l->first_pipe_idx_in_plane = DML2_MAX_PLANES; in dcn6_rq_dlg_get_dlg_reg()
1533 memset(l->stream_visited, 0, DML2_MAX_PLANES * sizeof(bool)); in dcn6_calculate_stutter_efficiency()
1643 unsigned int bytes_required_l[dml2_pstate_type_count][DML2_MAX_PLANES], in dcn6_calculate_excess_vactive_bandwidth_required() argument
1644 unsigned int bytes_required_c[dml2_pstate_type_count][DML2_MAX_PLANES], in dcn6_calculate_excess_vactive_bandwidth_required() argument
1673 const unsigned int v_blank_start[DML2_MAX_PLANES], in dcn6_calculate_pstate_schedule_windows() argument
1674 const unsigned int v_blank_end[DML2_MAX_PLANES], in dcn6_calculate_pstate_schedule_windows() argument
1675 const double otg_vline_time_us[DML2_MAX_PLANES], in dcn6_calculate_pstate_schedule_windows() argument
1676 const double det_fill_delay_us[DML2_MAX_PLANES], in dcn6_calculate_pstate_schedule_windows() argument
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H A Ddml2_core_dcn5_calcs_dchub.c489 bool DETPieceAssignedToThisSurfaceAlready[DML2_MAX_PLANES]; in dcn5_calculate_det_buffer_size()
692 unsigned int MaximumSwathHeightY[DML2_MAX_PLANES] = { 0 }; in dcn5_calculate_swath_and_det_configuration()
693 unsigned int MaximumSwathHeightC[DML2_MAX_PLANES] = { 0 }; in dcn5_calculate_swath_and_det_configuration()
694 unsigned int RoundedUpSwathSizeBytesY[DML2_MAX_PLANES] = { 0 }; in dcn5_calculate_swath_and_det_configuration()
695 unsigned int RoundedUpSwathSizeBytesC[DML2_MAX_PLANES] = { 0 }; in dcn5_calculate_swath_and_det_configuration()
1890 double DCFClkDeepSleepPerSurface[DML2_MAX_PLANES]; in dcn5_calculate_dcfclk_deep_sleep()
5138 memset(l->stream_visited, 0, DML2_MAX_PLANES * sizeof(bool)); in dcn5_calculate_stutter_efficiency()
5527 DML_ASSERT(l->plane_idx < DML2_MAX_PLANES); in dcn5_rq_dlg_get_dlg_reg()
5541 if (l->plane_idx < DML2_MAX_PLANES) { in dcn5_rq_dlg_get_dlg_reg()
5578 l->first_pipe_idx_in_plane = DML2_MAX_PLANES; in dcn5_rq_dlg_get_dlg_reg()
H A Ddml2_core_dcn5_funcs_mode_programming.c1702 for (unsigned int plane_idx = 0; plane_idx < DML2_MAX_PLANES; plane_idx++) { in dcn5_pack_mode_programming_params()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/
H A Ddml2_pmo_dcn6_stage_optimizers.c75 for (i = 0; i < DML2_MAX_PLANES; i++) { in all_planes_match_method()
238 memset(s->sorted_group_gtl_disallow_index, 0, sizeof(unsigned int) * DML2_MAX_PLANES); in dcn6_is_pstate_schedulable()
537 for (i = 0; i < DML2_MAX_PLANES; i++) { in dcn6_get_vactive_latency_hiding()
555 for (i = 0; i < DML2_MAX_PLANES; i++) { in dcn6_get_vactive_det_fill_delay_us()
573 for (i = 0; i < DML2_MAX_PLANES; i++) { in dcn6_get_required_vactive_det_fill_delay_us()
1082 sizeof(struct dml2_pstate_meta) * DML2_MAX_PLANES); in setup_optimized_worksheet_for_uclk_pstate()