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Searched refs:DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_sh_mask.h7750 #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x5 macro
H A Ddce_11_0_sh_mask.h6690 #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x5 macro
H A Ddce_10_0_sh_mask.h6794 #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x5 macro
H A Ddce_11_2_sh_mask.h7770 #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x5 macro
H A Ddce_12_0_sh_mask.h4696 #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h1374 #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT … macro
H A Ddcn_1_0_sh_mask.h3666 #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT … macro
H A Ddcn_3_0_1_sh_mask.h2317 #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h2172 #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT … macro
H A Ddcn_3_1_2_sh_mask.h1809 #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT … macro
H A Ddcn_3_1_5_sh_mask.h1318 #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT … macro
H A Ddcn_3_1_6_sh_mask.h2374 #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT … macro
H A Ddcn_3_1_4_sh_mask.h10427 #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h2243 #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h2440 #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h2315 #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT … macro