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Searched refs:DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h5963 #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x00000020L macro
H A Ddce_8_0_sh_mask.h7749 #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x20 macro
H A Ddce_11_0_sh_mask.h6689 #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x20 macro
H A Ddce_10_0_sh_mask.h6793 #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x20 macro
H A Ddce_11_2_sh_mask.h7769 #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x20 macro
H A Ddce_12_0_sh_mask.h4702 #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h3672 #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK … macro
H A Ddcn_3_0_1_sh_mask.h2323 #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK … macro
H A Ddcn_2_1_0_sh_mask.h2178 #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK … macro
H A Ddcn_2_0_0_sh_mask.h2446 #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK … macro