Searched refs:DIV_CLK_MPLL_RP_CPU_NORMAL_0 (Results 1 – 2 of 2) sorted by relevance
9 #define DIV_CLK_MPLL_RP_CPU_NORMAL_0 0 macro
485 SG2042_DIV_HWS(DIV_CLK_MPLL_RP_CPU_NORMAL_0,