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Searched refs:DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_sh_mask.h7133 #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x80000 macro
H A Ddce_11_0_sh_mask.h15276 #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x80000 macro
H A Ddce_10_0_sh_mask.h15128 #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x80000 macro
H A Ddce_11_2_sh_mask.h15938 #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x80000 macro
H A Ddce_12_0_sh_mask.h8223 #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h2702 #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK … macro
H A Ddcn_1_0_sh_mask.h5161 #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK … macro
H A Ddcn_3_0_1_sh_mask.h4067 #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK … macro
H A Ddcn_3_2_1_sh_mask.h1347 #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK … macro
H A Ddcn_2_1_0_sh_mask.h3880 #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK … macro
H A Ddcn_3_5_1_sh_mask.h8354 #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK … macro
H A Ddcn_3_5_0_sh_mask.h8375 #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK … macro
H A Ddcn_3_1_2_sh_mask.h3837 #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK … macro
H A Ddcn_3_1_6_sh_mask.h4404 #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK … macro
H A Ddcn_3_1_4_sh_mask.h12191 #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK … macro
H A Ddcn_3_0_2_sh_mask.h4034 #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK … macro
H A Ddcn_2_0_0_sh_mask.h4148 #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK … macro
H A Ddcn_3_0_0_sh_mask.h4143 #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK … macro
H A Ddcn_3_2_0_sh_mask.h1349 #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK … macro