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Searched refs:DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_sh_mask.h7025 #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x80000 macro
H A Ddce_11_0_sh_mask.h15168 #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x80000 macro
H A Ddce_10_0_sh_mask.h15020 #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x80000 macro
H A Ddce_11_2_sh_mask.h15830 #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x80000 macro
H A Ddce_12_0_sh_mask.h8113 #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h2624 #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK … macro
H A Ddcn_1_0_sh_mask.h5066 #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK … macro
H A Ddcn_3_0_1_sh_mask.h3989 #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK … macro
H A Ddcn_3_2_1_sh_mask.h1269 #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK … macro
H A Ddcn_2_1_0_sh_mask.h3785 #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK … macro
H A Ddcn_3_5_1_sh_mask.h8278 #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK … macro
H A Ddcn_3_5_0_sh_mask.h8299 #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK … macro
H A Ddcn_3_1_2_sh_mask.h3759 #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK … macro
H A Ddcn_3_1_6_sh_mask.h4326 #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK … macro
H A Ddcn_3_1_4_sh_mask.h12113 #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK … macro
H A Ddcn_3_0_2_sh_mask.h3956 #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK … macro
H A Ddcn_2_0_0_sh_mask.h4053 #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK … macro
H A Ddcn_3_0_0_sh_mask.h4065 #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK … macro
H A Ddcn_3_2_0_sh_mask.h1271 #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK … macro