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Searched refs:DISP_CC_MDSS_PCLK1_CLK_SRC (Results 1 – 19 of 19) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dqcom,dispcc-sdm845.h28 #define DISP_CC_MDSS_PCLK1_CLK_SRC 18 macro
H A Dqcom,dispcc-sm8350.h49 #define DISP_CC_MDSS_PCLK1_CLK_SRC 39 macro
H A Dqcom,dispcc-sm8250.h49 #define DISP_CC_MDSS_PCLK1_CLK_SRC 39 macro
H A Dqcom,dispcc-sm8150.h49 #define DISP_CC_MDSS_PCLK1_CLK_SRC 39 macro
H A Dqcom,x1e80100-dispcc.h76 #define DISP_CC_MDSS_PCLK1_CLK_SRC 66 macro
H A Dqcom,dispcc-sc8280xp.h78 #define DISP_CC_MDSS_PCLK1_CLK_SRC 68 macro
H A Dqcom,sm8550-dispcc.h79 #define DISP_CC_MDSS_PCLK1_CLK_SRC 69 macro
H A Dqcom,sm8450-dispcc.h78 #define DISP_CC_MDSS_PCLK1_CLK_SRC 68 macro
/linux/drivers/clk/qcom/
H A Ddispcc-sdm845.c807 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
H A Ddispcc-sm8250.c1208 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
H A Ddispcc-sc8280xp.c2947 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp0_cc_mdss_pclk1_clk_src.clkr,
3029 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp1_cc_mdss_pclk1_clk_src.clkr,
H A Ddispcc-x1e80100.c1607 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
H A Ddispcc-sm8550.c1717 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
H A Ddispcc-sm8450.c1748 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
/linux/arch/arm64/boot/dts/qcom/
H A Dsm8350.dtsi2812 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
H A Dsm8150.dtsi4072 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
H A Dsm8550.dtsi3165 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
H A Dsm8650.dtsi3676 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
H A Dsm8250.dtsi4952 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;