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Searched refs:DISP_CC_MDSS_CORE_INT2_BCR (Results 1 – 9 of 9) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dqcom,sm4450-dispcc.h48 #define DISP_CC_MDSS_CORE_INT2_BCR 1 macro
H A Dqcom,x1e80100-dispcc.h91 #define DISP_CC_MDSS_CORE_INT2_BCR 1 macro
H A Dqcom,sm8550-dispcc.h94 #define DISP_CC_MDSS_CORE_INT2_BCR 1 macro
H A Dqcom,sm8450-dispcc.h96 #define DISP_CC_MDSS_CORE_INT2_BCR 1 macro
/linux/drivers/clk/qcom/
H A Ddispcc-sm4450.c713 [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
H A Ddispcc-x1e80100.c1621 [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
H A Ddispcc-sm8450.c1766 [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
H A Ddispcc-sm8550.c1732 [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
H A Ddispcc-sm8750.c1871 [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },