Home
last modified time | relevance | path

Searched refs:DISP_CC_MDSS_BYTE1_CLK_SRC (Results 1 – 19 of 19) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dqcom,dispcc-sdm845.h16 #define DISP_CC_MDSS_BYTE1_CLK_SRC 6 macro
H A Dqcom,dispcc-sm8350.h17 #define DISP_CC_MDSS_BYTE1_CLK_SRC 7 macro
H A Dqcom,dispcc-sm8250.h17 #define DISP_CC_MDSS_BYTE1_CLK_SRC 7 macro
H A Dqcom,dispcc-sm8150.h17 #define DISP_CC_MDSS_BYTE1_CLK_SRC 7 macro
H A Dqcom,x1e80100-dispcc.h19 #define DISP_CC_MDSS_BYTE1_CLK_SRC 9 macro
H A Dqcom,dispcc-sc8280xp.h22 #define DISP_CC_MDSS_BYTE1_CLK_SRC 12 macro
H A Dqcom,sm8550-dispcc.h19 #define DISP_CC_MDSS_BYTE1_CLK_SRC 9 macro
H A Dqcom,sm8450-dispcc.h18 #define DISP_CC_MDSS_BYTE1_CLK_SRC 8 macro
/linux/drivers/clk/qcom/
H A Ddispcc-sdm845.c780 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
H A Ddispcc-sm8250.c1166 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
H A Ddispcc-sc8280xp.c2891 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp0_cc_mdss_byte1_clk_src.clkr,
2973 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp1_cc_mdss_byte1_clk_src.clkr,
H A Ddispcc-x1e80100.c1547 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
H A Ddispcc-sm8550.c1655 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
H A Ddispcc-sm8450.c1686 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
/linux/arch/arm64/boot/dts/qcom/
H A Dsm8350.dtsi2811 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
H A Dsm8150.dtsi4071 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
H A Dsm8550.dtsi3164 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
H A Dsm8650.dtsi3675 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
H A Dsm8250.dtsi4952 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;