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Searched refs:DDIV_DIVCTL_WEN (Results 1 – 1 of 1) sorted by relevance

/linux/drivers/clk/renesas/
H A Drzv2h-cpg.c68 #define DDIV_DIVCTL_WEN(shift) BIT((shift) + 16) macro
321 val = readl(priv->base + ddiv.offset) | DDIV_DIVCTL_WEN(shift); in rzv2h_cpg_plldsi_div_set_rate()
805 val = readl(divider->reg) | DDIV_DIVCTL_WEN(divider->shift); in rzv2h_ddiv_set_rate()