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Searched refs:DC__VOLTAGE_STATES (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_vba.h317 …double ActiveDRAMClockChangeLatencyMarginPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];// DML …
536 unsigned int PrefetchMode[DC__VOLTAGE_STATES][2];
537 unsigned int PrefetchModePerState[DC__VOLTAGE_STATES][2];
599 double DCFCLKPerState[DC__VOLTAGE_STATES];
600 double DCFCLKState[DC__VOLTAGE_STATES][2];
601 double FabricClockPerState[DC__VOLTAGE_STATES];
602 double SOCCLKPerState[DC__VOLTAGE_STATES];
603 double PHYCLKPerState[DC__VOLTAGE_STATES];
604 double DTBCLKPerState[DC__VOLTAGE_STATES];
605 double MaxDppclk[DC__VOLTAGE_STATES];
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H A Ddc_features.h39 #define DC__VOLTAGE_STATES 40 macro
H A Ddisplay_mode_structs.h182 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c2139 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()
2140 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()
2141 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()
2142 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()
2144 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; in dcn30_update_bw_bounding_box()
2230 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()
2244 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()
2249 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn30_update_bw_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c2775 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; in build_synthetic_soc_states()
3118 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn32_update_bw_bounding_box_fpu()
3119 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn32_update_bw_bounding_box_fpu()
3120 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; in dcn32_update_bw_bounding_box_fpu()
3121 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn32_update_bw_bounding_box_fpu()
3125 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; in dcn32_update_bw_bounding_box_fpu()
3194 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn32_update_bw_bounding_box_fpu()
3208 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn32_update_bw_bounding_box_fpu()
3213 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn32_update_bw_bounding_box_fpu()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc.h1863 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];