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Searched refs:DC_LOG_HW_LINK_TRAINING (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_training.c198 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n", in dp_initialize_scrambling_data_symbols()
215 DC_LOG_HW_LINK_TRAINING("%s: Using DP training pattern TPS1\n", __func__); in dp_training_pattern_to_dpcd_training_pattern()
219 DC_LOG_HW_LINK_TRAINING("%s: Using DP training pattern TPS2\n", __func__); in dp_training_pattern_to_dpcd_training_pattern()
223 DC_LOG_HW_LINK_TRAINING("%s: Using DP training pattern TPS3\n", __func__); in dp_training_pattern_to_dpcd_training_pattern()
227 DC_LOG_HW_LINK_TRAINING("%s: Using DP training pattern TPS4\n", __func__); in dp_training_pattern_to_dpcd_training_pattern()
231 DC_LOG_HW_LINK_TRAINING("%s: Using DP 128b/132b training pattern TPS1\n", __func__); in dp_training_pattern_to_dpcd_training_pattern()
235 DC_LOG_HW_LINK_TRAINING("%s: Using DP 128b/132b training pattern TPS2\n", __func__); in dp_training_pattern_to_dpcd_training_pattern()
239 DC_LOG_HW_LINK_TRAINING("%s: Using DP 128b/132b training pattern TPS2 CDS\n", in dp_training_pattern_to_dpcd_training_pattern()
244 DC_LOG_HW_LINK_TRAINING("%s: Using DP training pattern videoidle\n", __func__); in dp_training_pattern_to_dpcd_training_pattern()
249 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n", in dp_training_pattern_to_dpcd_training_pattern()
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H A Dlink_dp_training_dpia.c106 DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) configuring\n - LTTPR mode(%d)\n", in dpia_configure_link()
251 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n", in dpcd_set_lt_pattern()
257 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n", in dpcd_set_lt_pattern()
401 DC_LOG_HW_LINK_TRAINING("%s: Clock recovery OK\n", __func__); in dpia_training_cr_non_transparent()
430 DC_LOG_HW_LINK_TRAINING( in dpia_training_cr_non_transparent()
505 DC_LOG_HW_LINK_TRAINING("%s: Clock recovery OK\n", __func__); in dpia_training_cr_transparent()
533 DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) clock recovery\n -hop(%d)\n - result(%d)\n - retries(%d)\n", in dpia_training_cr_transparent()
701 DC_LOG_HW_LINK_TRAINING( in dpia_training_eq_non_transparent()
788 DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) equalization\n - hop(%d)\n - result(%d)\n - retries(%d)\n", in dpia_training_eq_transparent()
904 DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) end\n - hop(%d)\n - result(%d)\n - LTTPR mode(%d)\n", in dpia_training_end()
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H A Dlink_dp_training_128b_132b.c48 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X TX_FFE_PRESET_VALUE = %x\n", in dpcd_128b_132b_set_lane_settings()
217 DC_LOG_HW_LINK_TRAINING("%s: Channel EQ done.\n", __func__); in dp_perform_128b_132b_link_training()
223 DC_LOG_HW_LINK_TRAINING("%s: CDS done.\n", __func__); in dp_perform_128b_132b_link_training()
H A Dlink_dp_training_8b_10b.c233 DC_LOG_HW_LINK_TRAINING("%s: Clock recovery OK\n", __func__); in perform_8b_10b_clock_recovery_sequence()
395 DC_LOG_HW_LINK_TRAINING("%s: Channel EQ done.\n", __func__); in dp_perform_8b_10b_link_training()
418 DC_LOG_HW_LINK_TRAINING("%s: Channel EQ done.\n", __func__); in dp_perform_8b_10b_link_training()
H A Dlink_dp_training_fixed_vs_pe_retimer.c290 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n", in dp_perform_fixed_vs_pe_training_sequence()
H A Dlink_dp_capability.c2167 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR, max_lane count %d max_link rate %d \n", in dp_get_max_link_cap()
/linux/drivers/gpu/drm/amd/display/include/
H A Dlogger_types.h37 #define DC_LOG_HW_LINK_TRAINING(...) pr_debug("[HW_LINK_TRAINING]:"__VA_ARGS__) macro