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Searched refs:DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h3858 #define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x00000000 macro
H A Ddce_8_0_sh_mask.h3330 #define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0 macro
H A Ddce_11_0_sh_mask.h3324 #define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0 macro
H A Ddce_10_0_sh_mask.h3252 #define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0 macro
H A Ddce_11_2_sh_mask.h3574 #define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0 macro
H A Ddce_12_0_sh_mask.h9415 #define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h4927 #define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT … macro
H A Ddcn_3_0_1_sh_mask.h3859 #define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h3644 #define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT … macro
H A Ddcn_3_5_1_sh_mask.h8160 #define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT … macro
H A Ddcn_3_5_0_sh_mask.h8181 #define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h3912 #define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT … macro
H A Ddcn_4_1_0_sh_mask.h1328 #define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT … macro