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Searched refs:DCN_BASE__INST0_SEG1 (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_dcn316.c34 #define DCN_BASE__INST0_SEG1 0x000000C0 macro
H A Ddmub_dcn315.c34 #define DCN_BASE__INST0_SEG1 0x000000C0 macro
H A Ddmub_dcn314.c34 #define DCN_BASE__INST0_SEG1 0x000000C0 macro
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn315/
H A Dhw_factory_dcn315.c46 #define DCN_BASE__INST0_SEG1 0x000000C0 macro
H A Dhw_translate_dcn315.c39 #define DCN_BASE__INST0_SEG1 0x000000C0 macro
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn315/
H A Dirq_service_dcn315.c39 #define DCN_BASE__INST0_SEG1 0x000000C0 macro
/linux/drivers/gpu/drm/amd/include/
H A Dnavi10_ip_offset.h268 #define DCN_BASE__INST0_SEG1 0x000000C0 macro
H A Ddimgrey_cavefish_ip_offset.h362 #define DCN_BASE__INST0_SEG1 0x000000C0 macro
H A Dsienna_cichlid_ip_offset.h369 #define DCN_BASE__INST0_SEG1 0x000000C0 macro
H A Dbeige_goby_ip_offset.h440 #define DCN_BASE__INST0_SEG1 0x000000C0 macro
H A Dvega10_ip_offset.h304 #define DCN_BASE__INST0_SEG1 0x000000C0 macro
H A Drenoir_ip_offset.h1368 #define DCN_BASE__INST0_SEG1 0x000000C0 macro
H A Dyellow_carp_offset.h386 #define DCN_BASE__INST0_SEG1 0x000000C0 macro
H A Dvangogh_ip_offset.h451 #define DCN_BASE__INST0_SEG1 0x000000C0 macro
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c46 #define DCN_BASE__INST0_SEG1 0x000000C0 macro