| /linux/include/dt-bindings/clock/ |
| H A D | rk3128-cru.h | 71 #define DCLK_VOP 190 macro
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| H A D | rk3228-cru.h | 70 #define DCLK_VOP 190 macro
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| H A D | rockchip,rk3506-cru.h | 225 #define DCLK_VOP 212 macro
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| H A D | rv1108-cru.h | 83 #define DCLK_VOP 187 macro
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| H A D | rk3308-cru.h | 129 #define DCLK_VOP 125 macro
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| H A D | rk3368-cru.h | 84 #define DCLK_VOP 190 macro
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| H A D | rockchip,rv1126b-cru.h | 81 #define DCLK_VOP 68 macro
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| H A D | rockchip,rv1126-cru.h | 221 #define DCLK_VOP 154 macro
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| /linux/arch/arm/boot/dts/rockchip/ |
| H A D | rk3128.dtsi | 233 <&cru DCLK_VOP>,
291 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_VOP>,
594 clocks = <&cru PCLK_HDMI>, <&cru DCLK_VOP>;
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| H A D | rv1126.dtsi | 214 <&cru DCLK_VOP>,
586 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
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| H A D | rk322x.dtsi | 222 <&cru DCLK_VOP>,
667 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
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| /linux/drivers/clk/rockchip/ |
| H A D | clk-rk3128.c | 331 COMPOSITE(DCLK_VOP, "dclk_vop", mux_sclk_vop_src_p, 0,
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| H A D | clk-rk3228.c | 412 MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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| H A D | clk-rv1108.c | 442 MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, CLK_SET_RATE_PARENT,
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| H A D | clk-rk3368.c | 450 COMPOSITE(DCLK_VOP, "dclk_vop", mux_pll_src_cpll_gpll_npll_p, 0,
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| H A D | clk-rk3506.c | 679 COMPOSITE(DCLK_VOP, "dclk_vop", dclk_vop_parents_p, 0,
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| H A D | clk-rk3308.c | 457 GATE(DCLK_VOP, "dclk_vop", "dclk_vop_mux", 0,
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| H A D | clk-rv1126.c | 753 GATE(DCLK_VOP, "dclk_vop", "dclk_vop_mux", 0,
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| H A D | clk-rv1126b.c | 386 COMPOSITE(DCLK_VOP, "dclk_vop", mux_gpll_cpll_p, 0,
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| /linux/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3368.dtsi | 669 <&cru DCLK_VOP>,
862 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
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