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Searched refs:DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_11_2_sh_mask.h1751 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK 0x8 macro
H A Ddce_12_0_sh_mask.h2652 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_sh_mask.h142 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK … macro
H A Ddcn_3_0_3_sh_mask.h530 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK … macro
H A Ddcn_1_0_sh_mask.h2016 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK … macro
H A Ddcn_3_0_1_sh_mask.h860 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK … macro
H A Ddcn_2_1_0_sh_mask.h472 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK … macro
H A Ddcn_3_5_1_sh_mask.h6423 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK … macro
H A Ddcn_3_5_0_sh_mask.h6444 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK … macro
H A Ddcn_3_1_2_sh_mask.h792 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK … macro
H A Ddcn_3_1_5_sh_mask.h295 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK … macro
H A Ddcn_3_1_6_sh_mask.h1329 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK … macro
H A Ddcn_3_1_4_sh_mask.h8260 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK … macro
H A Ddcn_3_0_2_sh_mask.h585 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK … macro
H A Ddcn_2_0_0_sh_mask.h590 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK … macro
H A Ddcn_3_0_0_sh_mask.h571 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK … macro