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Searched refs:DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_11_2_sh_mask.h1749 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK 0x4 macro
H A Ddce_12_0_sh_mask.h2651 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_sh_mask.h141 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK … macro
H A Ddcn_3_0_3_sh_mask.h529 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK … macro
H A Ddcn_1_0_sh_mask.h2015 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK … macro
H A Ddcn_3_0_1_sh_mask.h859 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK … macro
H A Ddcn_2_1_0_sh_mask.h471 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK … macro
H A Ddcn_3_5_1_sh_mask.h6422 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK … macro
H A Ddcn_3_5_0_sh_mask.h6443 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK … macro
H A Ddcn_3_1_2_sh_mask.h791 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK … macro
H A Ddcn_3_1_5_sh_mask.h294 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK … macro
H A Ddcn_3_1_6_sh_mask.h1328 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK … macro
H A Ddcn_3_1_4_sh_mask.h8259 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK … macro
H A Ddcn_3_0_2_sh_mask.h584 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK … macro
H A Ddcn_2_0_0_sh_mask.h589 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK … macro
H A Ddcn_3_0_0_sh_mask.h570 #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK … macro