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/linux/Documentation/hwmon/
H A Dcoretemp.rst5 * All Intel Core family
11 - 0xe (Pentium M DC), 0xf (Core 2 DC 65nm),
12 - 0x16 (Core 2 SC 65nm), 0x17 (Penryn 45nm),
49 tempX_input Core temperature (in millidegrees Celsius).
54 tempX_label Contains string "Core X", where X is processor
70 22nm Core i5/i7 Processors
81 32nm Core i3/i5/i7 Processors
88 32nm Core i7 Extreme Processors
103 45nm Xeon Processors 5400 Quad-Core
109 45nm Xeon Processors 5200 Dual-Core
[all …]
H A Dk8temp.rst36 temp1_input temperature of Core 0 and "place" 0
37 temp2_input temperature of Core 0 and "place" 1
38 temp3_input temperature of Core 1 and "place" 0
39 temp4_input temperature of Core 1 and "place" 1
H A Dsmpro-hwmon.rst58 temp4_input millicelsius RO Max temperature reported among Core VRDs
76 in0_input millivolts RO Core voltage
81 cur1_input milliamperes RO Core VRD current
86 power1_input microwatts RO Core VRD power
H A Dk10temp.rst8 Socket F: Quad-Core/Six-Core/Embedded Opteron (but see below)
10 Socket AM2+: Quad-Core Opteron, Phenom (II) X3/X4, Athlon X2 (but see below)
12 Socket AM3: Quad-Core Opteron, Athlon/Phenom II X2/X3/X4, Sempron II
132 Core Complex Die (CCD) temperatures. Up to 8 such temperatures are reported
/linux/samples/rust/
H A Drust_driver_usb.rs6 use kernel::{device, device::Core, prelude::*, sync::aref::ARef, usb};
24 intf: &usb::Interface<Core>, in probe() argument
28 let dev: &device::Device<Core> = intf.as_ref(); in probe()
34 fn disconnect(intf: &usb::Interface<Core>, _data: Pin<&Self>) { in disconnect() argument
35 let dev: &device::Device<Core> = intf.as_ref(); in disconnect()
H A Drust_driver_i2c.rs8 device::Core,
45 idev: &i2c::I2cClient<Core>, in probe() argument
59 fn shutdown(idev: &i2c::I2cClient<Core>, _this: Pin<&Self>) { in shutdown() argument
63 fn unbind(idev: &i2c::I2cClient<Core>, _this: Pin<&Self>) { in unbind() argument
H A Drust_driver_pci.rs7 use kernel::{c_str, device::Core, devres::Devres, pci, prelude::*, sync::aref::ARef};
68 fn probe(pdev: &pci::Device<Core>, info: &Self::IdInfo) -> impl PinInit<Self, Error> { in probe() argument
98 fn unbind(pdev: &pci::Device<Core>, this: Pin<&Self>) { in unbind() argument
H A Drust_driver_auxiliary.rs9 device::{Bound, Core},
38 fn probe(adev: &auxiliary::Device<Core>, _info: &Self::IdInfo) -> impl PinInit<Self, Error> { in probe() argument
72 fn probe(pdev: &pci::Device<Core>, _info: &Self::IdInfo) -> impl PinInit<Self, Error> { in probe() argument
H A Drust_debugfs.rs42 use kernel::{acpi, device::Core, of, platform, str::CString, types::ARef};
110 pdev: &platform::Device<Core>, in probe() argument
135 fn new(pdev: &platform::Device<Core>) -> impl PinInit<Self, Error> + '_ { in new()
/linux/drivers/usb/dwc3/
H A DKconfig4 tristate "DesignWare USB3 DRD Core Support"
11 USB controller based on the DesignWare USB3 IP Core.
74 Exynos5800, Exynos5433, Exynos7) ship with one DesignWare Core USB3
82 If you're using the DesignWare Core IP with a PCIe (but not HAPS
90 If you're using the DesignWare Core IP with a Synopsys PCIe HAPS
126 STMicroelectronics SoCs with one DesignWare Core USB3 IP
137 Some Qualcomm SoCs use DesignWare Core IP for USB2/3
149 NXP iMX8M Plus SoC use DesignWare Core IP for USB2/3
158 Support Xilinx SoCs with DesignWare Core USB3 IP.
167 Support TI's AM62 platforms with DesignWare Core USB3 IP.
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/linux/Documentation/arch/x86/
H A Dtopology.rst91 - On AMD, the Node ID or Core Complex ID containing the Last Level
108 AMDs nomenclature for CMT threads is "Compute Unit Core". The kernel always
156 1) CPUID leaf 0x80000026 [Extended CPU Topology] (Core::X86::Cpuid::ExCpuTopology)
159 and provides the topology information of Core, Complex, CCD (Die), and
167 the level describes - Core, Complex, CCD(Die), or the Socket.
180 2) CPUID leaf 0x0000000B [Extended Topology Enumeration] (Core::X86::Cpuid::ExtTopEnum)
201 3) CPUID leaf 0x80000008 ECX [Size Identifiers] (Core::X86::Cpuid::SizeId)
225 4) CPUID leaf 0x8000001E [Extended APIC ID, Core Identifiers, Node Identifiers]
226 (Core::X86::Cpuid::{ExtApicId,CoreId,NodeId})
230 [Feature Identifiers] (Core::X86::Cpuid::FeatureExtIdEcx).
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/linux/Documentation/arch/arm/
H A Dmarvell.rst31 Core:
79 Core:
111 Core:
132 Core:
151 Core:
160 Core:
177 Core:
187 Core:
202 Core:
222 Core: ARM Cortex A72
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/linux/Documentation/networking/caif/
H A Dlinux_caif.rst32 * CAIF Core Protocol Implementation
47 ! +------+ <- CAIF Core Protocol
49 ! ! Core !
63 CAIF Core Protocol Layer
66 CAIF Core layer implements the CAIF protocol as defined by ST-Ericsson.
75 The Core CAIF implementation contains:
180 CAIF Core protocol. The IP Interface and CAIF socket have an instance of
181 'struct cflayer', just like the CAIF Core protocol stack.
/linux/drivers/gpu/nova-core/
H A Ddriver.rs6 device::Core,
72 fn probe(pdev: &pci::Device<Core>, _info: &Self::IdInfo) -> impl PinInit<Self, Error> { in probe() argument
101 fn unbind(pdev: &pci::Device<Core>, this: Pin<&Self>) { in unbind() argument
H A DKconfig2 tristate "Nova Core GPU driver"
10 Choose this if you want to build the Nova Core driver for Nvidia
/linux/rust/kernel/
H A Ddevice.rs553 pub struct Core; struct
588 impl Sealed for super::Core {} implementation
594 impl DeviceContext for Core {} implementation
670 $crate::device::CoreInternal => $crate::device::Core
677 $crate::device::Core => $crate::device::Bound
707 ::kernel::__impl_device_context_into_aref!($crate::device::Core, $device);
/linux/Documentation/devicetree/bindings/display/ti/
H A Dti,omap-dss.txt11 The OMAP Display Subsystem (DSS) hardware consists of DSS Core, DISPC module and
12 a number of encoder modules. All DSS versions contain DSS Core and DISPC, but
15 The DSS Core is the parent of the other DSS modules, and manages clock routing,
27 The DSS Core and the encoders have video port outputs. The structure of the
90 DSS Core --(MIPI DPI)--> TFP410 --(DVI)--> DVI Connector
/linux/Documentation/ABI/testing/
H A Dsysfs-bus-platform-devices-ampere-smpro39 …| CPM (core) | 0 | 2 | Armv8 Core 1 | CPM # …
154 …| Core's CE | /sys/bus/platform/devices/smpro-errmon.*/error_core_ce | Core has CE error …
156 …| Core's UE | /sys/bus/platform/devices/smpro-errmon.*/error_core_ue | Core has UE error …
192 …| Core's CE | /sys/bus/platform/devices/smpro-errmon.*/overflow_core_ce | Core CE error overflow…
194 …| Core's UE | /sys/bus/platform/devices/smpro-errmon.*/overflow_core_ue | Core UE error overflow…
/linux/arch/arm64/boot/dts/apple/
H A Ds5l8960x-pmgr.dtsi15 apple,always-on; /* Core device */
24 apple,always-on; /* Core device */
51 apple,always-on; /* Core device */
60 apple,always-on; /* Core device */
69 apple,always-on; /* Core device */
78 apple,always-on; /* Core device */
404 apple,always-on; /* Core device */
456 apple,always-on; /* Core device */
465 apple,always-on; /* Core device */
474 apple,always-on; /* Core device */
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H A Dt7001-pmgr.dtsi15 apple,always-on; /* Core device */
24 apple,always-on; /* Core device */
33 apple,always-on; /* Core device */
42 apple,always-on; /* Core device */
59 apple,always-on; /* Core device */
68 apple,always-on; /* Core device */
77 apple,always-on; /* Core device */
327 apple,always-on; /* Core device */
499 apple,always-on; /* Core device */
508 apple,always-on; /* Core device */
[all …]
/linux/Documentation/admin-guide/hw-vuln/
H A Dcore-scheduling.rst4 Core Scheduling
6 Core scheduling support allows userspace to define groups of tasks that can
18 full mitigation of cross-HT attacks is to disable Hyper Threading (HT). Core
34 Core scheduling support is enabled via the ``CONFIG_SCHED_CORE`` config option.
40 Core scheduling can be enabled via the ``PR_SCHED_CORE`` prctl interface.
151 Core scheduling maintains trust relationships amongst groups of tasks by
166 Core scheduling tries to guarantee that only trusted tasks run concurrently on a
173 Core scheduling selects only trusted tasks to run together. IPI is used to notify
185 Core scheduling cannot protect against MDS attacks between the siblings
194 Core scheduling cannot protect against an L1TF guest attacker exploiting a
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/linux/drivers/platform/x86/amd/hfi/
H A DKconfig7 bool "AMD Hetero Core Hardware Feedback Driver"
12 Select this option to enable the AMD Heterogeneous Core Hardware
/linux/sound/pcmcia/
H A DKconfig25 tristate "Sound Core PDAudioCF"
28 Say Y here to include support for Sound Core PDAudioCF
/linux/Documentation/driver-api/nfc/
H A Dnfc-hci.rst2 HCI backend for NFC Core
12 enables easy writing of HCI-based NFC drivers. The HCI layer runs as an NFC Core
13 backend, implementing an abstract nfc device and translating NFC Core API
19 HCI registers as an nfc device with NFC Core. Requests coming from userspace are
20 routed through netlink sockets to NFC Core and then to HCI. From this point,
26 and a translation will be forwarded to NFC Core as needed. There are hooks to
221 Any entrypoint in HCI called from NFC Core
277 Typically, such an event will be propagated to NFC Core from MSGRXWQ context.
282 Errors that occur synchronously with the execution of an NFC Core request are
304 command with that error, or notify NFC Core directly if no command is
[all …]
/linux/Documentation/devicetree/bindings/media/
H A Dimg-ir-rev1.txt16 1st: Core clock (defaults to 32.768KHz if omitted).
22 "core": Core clock.

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