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Searched refs:CXL_RESOURCE_NONE (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/cxl/core/
H A Dregs.c185 if (WARN_ON_ONCE(addr == CXL_RESOURCE_NONE)) in devm_cxl_iomap_block()
310 .resource = CXL_RESOURCE_NONE, in __cxl_find_regblock_instance()
340 map->resource = CXL_RESOURCE_NONE; in __cxl_find_regblock_instance()
491 if (WARN_ON_ONCE(rcrb == CXL_RESOURCE_NONE)) in cxl_rcrb_to_aer()
529 return CXL_RESOURCE_NONE; in cxl_rcrb_to_linkcap()
535 return CXL_RESOURCE_NONE; in cxl_rcrb_to_linkcap()
552 return CXL_RESOURCE_NONE; in cxl_rcrb_to_linkcap()
565 if (pos == CXL_RESOURCE_NONE) in cxl_dport_map_rcd_linkcap()
596 return CXL_RESOURCE_NONE; in __rcrb_to_component()
601 return CXL_RESOURCE_NONE; in __rcrb_to_component()
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H A Dport.c752 port->component_reg_phys = CXL_RESOURCE_NONE; in cxl_port_alloc()
772 if (component_reg_phys == CXL_RESOURCE_NONE) in cxl_setup_comp_regs()
963 port = devm_cxl_add_port(host, host, CXL_RESOURCE_NONE, NULL); in devm_cxl_add_root()
1149 if (rcrb == CXL_RESOURCE_NONE) { in __devm_cxl_add_dport()
1158 if (component_reg_phys == CXL_RESOURCE_NONE) { in __devm_cxl_add_dport()
1174 if (component_reg_phys != CXL_RESOURCE_NONE) in __devm_cxl_add_dport()
1189 port->component_reg_phys != CXL_RESOURCE_NONE) { in __devm_cxl_add_dport()
1195 port->component_reg_phys = CXL_RESOURCE_NONE; in __devm_cxl_add_dport()
1237 component_reg_phys, CXL_RESOURCE_NONE); in devm_cxl_add_dport()
1265 if (rcrb == CXL_RESOURCE_NONE) { in devm_cxl_add_rch_dport()
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H A Dhdm.c156 if (reg_map->resource == CXL_RESOURCE_NONE) { in devm_cxl_setup_hdm()
650 skip_start = CXL_RESOURCE_NONE; in __cxl_dpa_alloc()
663 if (skip_start == CXL_RESOURCE_NONE) in __cxl_dpa_alloc()
H A Dmbox.c1532 mds->cxlds.reg_map.resource = CXL_RESOURCE_NONE; in cxl_memdev_state_create()
/linux/drivers/cxl/
H A Dacpi.c590 if (ctx->base != CXL_RESOURCE_NONE) in cxl_get_chbs_iter()
618 .base = CXL_RESOURCE_NONE, in cxl_get_chbs()
672 if (ctx.base == CXL_RESOURCE_NONE) { in add_host_bridge_dport()
693 CXL_RESOURCE_NONE); in add_host_bridge_dport()
750 if (component_reg_phys != CXL_RESOURCE_NONE) in add_host_bridge_uport()
H A Dmem.c68 endpoint = devm_cxl_add_port(host, &cxlmd->dev, CXL_RESOURCE_NONE, in devm_cxl_add_endpoint()
H A Dpci.c485 .resource = CXL_RESOURCE_NONE, in cxl_rcrb_get_comp_regs()
494 if (component_reg_phys == CXL_RESOURCE_NONE) in cxl_rcrb_get_comp_regs()
H A Dcxl.h319 #define CXL_RESOURCE_NONE ((resource_size_t) -1) macro
/linux/tools/testing/cxl/test/
H A Dmock.c221 CXL_RESOURCE_NONE); in __wrap_devm_cxl_add_rch_dport()
H A Dcxl.c1064 CXL_RESOURCE_NONE); in mock_cxl_add_dport_by_dev()