Searched refs:CXL_RESOURCE_NONE (Results 1 – 7 of 7) sorted by relevance
567 if (ctx->base != CXL_RESOURCE_NONE) in cxl_get_chbs_iter()595 .base = CXL_RESOURCE_NONE, in cxl_get_chbs()649 if (ctx.base == CXL_RESOURCE_NONE) { in add_host_bridge_dport()670 CXL_RESOURCE_NONE); in add_host_bridge_dport()727 if (component_reg_phys != CXL_RESOURCE_NONE) in add_host_bridge_uport()
319 #define CXL_RESOURCE_NONE ((resource_size_t) -1) macro
742 port->component_reg_phys = CXL_RESOURCE_NONE; in cxl_port_alloc()762 if (component_reg_phys == CXL_RESOURCE_NONE) in cxl_setup_comp_regs()954 port = devm_cxl_add_port(host, host, CXL_RESOURCE_NONE, NULL); in devm_cxl_add_root()1191 if (rcrb == CXL_RESOURCE_NONE) { in DEFINE_FREE()1200 if (component_reg_phys == CXL_RESOURCE_NONE) { in DEFINE_FREE()1216 if (component_reg_phys != CXL_RESOURCE_NONE) in DEFINE_FREE()1270 component_reg_phys, CXL_RESOURCE_NONE); in devm_cxl_add_dport()1298 if (rcrb == CXL_RESOURCE_NONE) { in devm_cxl_add_rch_dport()1304 CXL_RESOURCE_NONE, rcrb); in devm_cxl_add_rch_dport()1555 return CXL_RESOURCE_NONE; in find_component_registers()
149 if (reg_map->resource == CXL_RESOURCE_NONE) { in devm_cxl_setup_hdm()643 skip_start = CXL_RESOURCE_NONE; in __cxl_dpa_alloc()656 if (skip_start == CXL_RESOURCE_NONE) in __cxl_dpa_alloc()
1539 mds->cxlds.reg_map.resource = CXL_RESOURCE_NONE; in cxl_memdev_state_create()
210 CXL_RESOURCE_NONE); in __wrap_devm_cxl_add_rch_dport()
1064 CXL_RESOURCE_NONE); in mock_cxl_add_dport_by_dev()