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Searched refs:CSR_DMW0_BASE (Results 1 – 4 of 4) sorted by relevance

/linux/arch/loongarch/include/asm/
H A Daddrspace.h29 #define IO_BASE CSR_DMW0_BASE
37 #define UNCACHE_BASE CSR_DMW0_BASE
42 #define WRITECOMBINE_BASE CSR_DMW0_BASE
H A Defi.h21 #define EFI_RT_VIRTUAL_OFFSET CSR_DMW0_BASE
H A Dloongarch.h930 #define CSR_DMW0_BASE (CSR_DMW0_VSEG << DMW_PABITS) macro
931 #define CSR_DMW0_INIT (CSR_DMW0_BASE | CSR_DMW0_PLV0)
947 #define CSR_DMW0_BASE (CSR_DMW0_VSEG << DMW_PABITS) macro
948 #define CSR_DMW0_INIT (CSR_DMW0_BASE | CSR_DMW0_PLV0)
/linux/arch/loongarch/mm/
H A Dcache.c37 uint64_t addr = CSR_DMW0_BASE; in flush_cache_leaf()