Searched refs:CSR_BASE (Results 1 – 2 of 2) sorted by relevance
83 #define CSR_BASE (0x000) macro85 #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */86 #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */87 #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */88 #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */89 #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack */90 #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */91 #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc */92 #define CSR_GP_CNTRL (CSR_BASE+0x024)95 #define CSR_INT_PERIODIC_REG (CSR_BASE+0x005)[all …]
170 #define CSR_BASE CSR_53C80_INTR macro