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Searched refs:CSR1 (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/media/pci/dt3155/
H A Ddt3155.c163 pd->regs + CSR1); in dt3155_start_streaming()
183 FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1); in dt3155_stop_streaming()
248 tmp = ioread32(ipd->regs + CSR1) & (FLD_CRPT_EVEN | FLD_CRPT_ODD); in dt3155_irq_handler_even()
253 ipd->regs + CSR1); in dt3155_irq_handler_even()
417 FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1); in dt3155_init_board()
421 iowrite32(FIFO_EN | SRST, pd->regs + CSR1); in dt3155_init_board()
H A Ddt3155.h36 #define CSR1 0x40 macro
/linux/drivers/net/ethernet/dec/tulip/
H A Dtulip.h107 CSR1 = 0x08, enumerator
564 iowrite32(0, ioaddr + CSR1); in tulip_tx_timeout_complete()
H A Dxircom_cb.c49 #define CSR1 0x08 macro
539 xw32(CSR1, 0); in trigger_transmit()
H A Dinterrupt.c688 iowrite32(0, ioaddr + CSR1); in tulip_interrupt()
H A Dtulip_core.c694 iowrite32(0, tp->base_addr + CSR1); in tulip_start_xmit()
1171 iowrite32(0, ioaddr + CSR1); in set_rx_mode()
/linux/drivers/net/ethernet/amd/
H A Dariadne.h63 #define CSR1 0x0100 /* - IADR[15:0] */ macro
H A Dsun3lance.c205 #define CSR1 1 /* init block addr (low) */ macro
498 REGA(CSR1) = dvma_vtob(&(MEM->init)); in lance_init_ring()
H A Datarilance.c305 #define CSR1 1 /* init block addr (low) */ macro
654 REGA( CSR1 ) = 0; in lance_open()
/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt2400pci.c878 reg = rt2x00mmio_register_read(rt2x00dev, CSR1); in rt2400pci_init_registers()
882 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); in rt2400pci_init_registers()
884 reg = rt2x00mmio_register_read(rt2x00dev, CSR1); in rt2400pci_init_registers()
887 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); in rt2400pci_init_registers()
H A Drt2400pci.h63 #define CSR1 0x0004 macro
H A Drt2500pci.c1016 reg = rt2x00mmio_register_read(rt2x00dev, CSR1); in rt2500pci_init_registers()
1020 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); in rt2500pci_init_registers()
1022 reg = rt2x00mmio_register_read(rt2x00dev, CSR1); in rt2500pci_init_registers()
1025 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); in rt2500pci_init_registers()
H A Drt2500pci.h74 #define CSR1 0x0004 macro
/linux/drivers/net/ethernet/renesas/
H A Dravb.h212 CSR1 = 0x0804, enumerator
H A Dravb_main.c507 ravb_write(ndev, CSR1_TIP4 | CSR1_TTCP4 | CSR1_TUDP4, CSR1); in ravb_csum_init_gbeth()
2548 ret = ravb_endisable_csum_gbeth(ndev, CSR1, val, CSR0_TPE); in ravb_set_features_gbeth()