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Searched refs:CRTC_REG (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_timing_generator.c48 #define CRTC_REG(reg) (reg + tg110->offsets.crtc) macro
99 addr = CRTC_REG(mmCRTC_STATUS); in dce110_timing_generator_is_in_vertical_blank()
111 uint32_t address = CRTC_REG(mmCRTC_CONTROL); in dce110_timing_generator_set_early_control()
140 dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value); in dce110_timing_generator_enable_crtc()
144 dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_LOCK), value); in dce110_timing_generator_enable_crtc()
156 uint32_t addr = CRTC_REG(mmCRTC_BLACK_COLOR); in dce110_timing_generator_program_blank_color()
192 uint32_t addr = CRTC_REG(mmCRTC_3D_STRUCTURE_CONTROL);
262 CRTC_REG(mmCRTC_COUNT_CONTROL)); in program_horz_count_by_2()
272 CRTC_REG(mmCRTC_COUNT_CONTROL), regval); in program_horz_count_by_2()
377 addr = CRTC_REG(mmCRTC_V_TOTAL_MIN); in dce110_timing_generator_set_drr()
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/linux/drivers/gpu/drm/amd/display/dc/dce60/
H A Ddce60_timing_generator.c83 #define CRTC_REG(reg) (reg + tg110->offsets.crtc) macro
130 uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL); in dce60_timing_generator_enable_advanced_request()
133 uint32_t addr2 = CRTC_REG(mmCRTC_CONTROL); in dce60_timing_generator_enable_advanced_request()
186 addr = CRTC_REG(mmCRTC_CONTROL); in dce60_is_tg_enabled()
/linux/drivers/gpu/drm/amd/display/dc/dce80/
H A Ddce80_timing_generator.c83 #define CRTC_REG(reg) (reg + tg110->offsets.crtc) macro
130 uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL); in dce80_timing_generator_enable_advanced_request()