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Searched refs:CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h3178 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000L macro
H A Dgfx_7_2_sh_mask.h2587 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000 macro
H A Dgfx_8_1_sh_mask.h3673 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000 macro
H A Dgfx_8_0_sh_mask.h3151 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h19414 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK … macro
H A Dgc_9_1_sh_mask.h20721 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK … macro
H A Dgc_9_2_1_sh_mask.h20648 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK … macro
H A Dgc_9_4_3_sh_mask.h22776 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK … macro
H A Dgc_9_4_2_sh_mask.h12875 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK … macro
H A Dgc_11_5_0_sh_mask.h22810 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK … macro
H A Dgc_11_0_0_sh_mask.h26798 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK … macro
H A Dgc_10_1_0_sh_mask.h27323 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK … macro
H A Dgc_11_0_3_sh_mask.h29298 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK … macro
H A Dgc_10_3_0_sh_mask.h25584 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK … macro