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Searched refs:CP_ME_CNTL__ME_HALT_MASK (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v7_0.c2369 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK |
4578 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK); in gfx_v7_0_soft_reset()
H A Dgfx_v6_0.c1941 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | in gfx_v6_0_cp_gfx_enable()
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2566 #define CP_ME_CNTL__ME_HALT_MASK 0x10000000L macro
H A Dgfx_7_2_sh_mask.h3053 #define CP_ME_CNTL__ME_HALT_MASK 0x10000000 macro
H A Dgfx_8_1_sh_mask.h4189 #define CP_ME_CNTL__ME_HALT_MASK 0x10000000 macro
H A Dgfx_8_0_sh_mask.h3667 #define CP_ME_CNTL__ME_HALT_MASK 0x10000000 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h1177 #define CP_ME_CNTL__ME_HALT_MASK … macro
H A Dgc_9_1_sh_mask.h1076 #define CP_ME_CNTL__ME_HALT_MASK … macro
H A Dgc_9_2_1_sh_mask.h1043 #define CP_ME_CNTL__ME_HALT_MASK … macro
H A Dgc_9_4_2_sh_mask.h1676 #define CP_ME_CNTL__ME_HALT_MASK … macro
H A Dgc_11_5_0_sh_mask.h20078 #define CP_ME_CNTL__ME_HALT_MASK … macro
H A Dgc_11_0_0_sh_mask.h24039 #define CP_ME_CNTL__ME_HALT_MASK … macro
H A Dgc_12_0_0_sh_mask.h13889 #define CP_ME_CNTL__ME_HALT_MASK … macro
H A Dgc_10_1_0_sh_mask.h6665 #define CP_ME_CNTL__ME_HALT_MASK … macro
H A Dgc_11_0_3_sh_mask.h26385 #define CP_ME_CNTL__ME_HALT_MASK … macro
H A Dgc_10_3_0_sh_mask.h6931 #define CP_ME_CNTL__ME_HALT_MASK 0x10000000L macro
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