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Searched refs:CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2361 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b macro
H A Dgfx_7_2_sh_mask.h1164 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b macro
H A Dgfx_8_1_sh_mask.h2010 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b macro
H A Dgfx_8_0_sh_mask.h1486 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h10766 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT … macro
H A Dgc_9_1_sh_mask.h12243 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h12047 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h2063 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT … macro
H A Dgc_11_5_0_sh_mask.h12001 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h15185 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT … macro
H A Dgc_12_0_0_sh_mask.h11669 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h17679 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h17340 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h15939 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT … macro