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Searched refs:CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2348 #define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L macro
H A Dgfx_7_2_sh_mask.h1169 #define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 macro
H A Dgfx_8_1_sh_mask.h2015 #define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 macro
H A Dgfx_8_0_sh_mask.h1491 #define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h10785 #define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK … macro
H A Dgc_9_1_sh_mask.h12262 #define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK … macro
H A Dgc_9_2_1_sh_mask.h12066 #define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK … macro
H A Dgc_9_4_3_sh_mask.h13791 #define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK … macro
H A Dgc_9_4_2_sh_mask.h2082 #define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK … macro
H A Dgc_11_5_0_sh_mask.h12023 #define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK … macro
H A Dgc_11_0_0_sh_mask.h15207 #define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK … macro
H A Dgc_12_0_0_sh_mask.h11691 #define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK … macro
H A Dgc_10_1_0_sh_mask.h17701 #define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK … macro
H A Dgc_11_0_3_sh_mask.h17362 #define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK … macro
H A Dgc_10_3_0_sh_mask.h15961 #define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK … macro