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Searched refs:CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2402 #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x00800000L macro
H A Dgfx_7_2_sh_mask.h1205 #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x800000 macro
H A Dgfx_8_1_sh_mask.h2063 #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x800000 macro
H A Dgfx_8_0_sh_mask.h1539 #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x800000 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11043 #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK … macro
H A Dgc_9_1_sh_mask.h12520 #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK … macro
H A Dgc_9_2_1_sh_mask.h12324 #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK … macro
H A Dgc_9_4_2_sh_mask.h2340 #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK … macro
H A Dgc_11_5_0_sh_mask.h12259 #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK … macro
H A Dgc_11_0_0_sh_mask.h15443 #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK … macro
H A Dgc_10_1_0_sh_mask.h17986 #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK … macro
H A Dgc_11_0_3_sh_mask.h17598 #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK … macro