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Searched refs:CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v6_0.c3288 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; in gfx_v6_0_set_priv_inst_fault_state()
3293 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; in gfx_v6_0_set_priv_inst_fault_state()
H A Dgfx_v7_0.c4723 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; in gfx_v7_0_set_eop_interrupt_state()
4728 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; in gfx_v7_0_set_eop_interrupt_state()
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2376 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L macro
H A Dgfx_7_2_sh_mask.h1179 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000 macro
H A Dgfx_8_1_sh_mask.h2031 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000 macro
H A Dgfx_8_0_sh_mask.h1507 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11009 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK … macro
H A Dgc_9_1_sh_mask.h12486 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK … macro
H A Dgc_9_2_1_sh_mask.h12290 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK … macro
H A Dgc_9_4_2_sh_mask.h2306 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK … macro
H A Dgc_11_5_0_sh_mask.h12235 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK … macro
H A Dgc_11_0_0_sh_mask.h15419 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK … macro
H A Dgc_12_0_0_sh_mask.h11855 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK … macro
H A Dgc_10_1_0_sh_mask.h17950 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK … macro
H A Dgc_11_0_3_sh_mask.h17574 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK … macro
H A Dgc_10_3_0_sh_mask.h16214 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK global() macro
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